EDBT 2026 Demo / reviewers in the wild / expert
Roberto Medina 0001
dblp:15/3696-1
· DBLP profile ↗
5ranked-venue papers
4as first author
2since 2021 · last 2023
0000-0003-1551-2765ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Embedded and real-time systems · 77% Energy-efficient computing · 11% Parallel and multicore computing · 8% |
Topics — the 12 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems › real-time scheduling
mixed-criticality scheduling |
0.8 | 2 | 2021 | Generalized Mixed-Criticality Static Scheduling for Periodic Directed Acyclic Graphs on Multi-Core Processors · IEEE Trans. Computers 2021 Scheduling Multi-periodic Mixed-Criticality DAGs on Multi-core Architectures · RTSS 2018 |
Embedded and real-time systems
real-time scheduling |
0.8 | 2 | 2021 | Generalized Mixed-Criticality Static Scheduling for Periodic Directed Acyclic Graphs on Multi-Core Processors · IEEE Trans. Computers 2021 Scheduling Multi-periodic Mixed-Criticality DAGs on Multi-core Architectures · RTSS 2018 |
Energy-efficient computing › power management
dynamic voltage and frequency scaling |
0.4 | 1 | 2019 | Work-in-Progress: Probabilistic System-Wide DVFS for Real-Time Embedded Systems · RTSS 2019 |
Embedded and real-time systems › energy-efficient embedded systems
energy-efficient real-time systems |
0.4 | 1 | 2019 | Work-in-Progress: Probabilistic System-Wide DVFS for Real-Time Embedded Systems · RTSS 2019 |
Embedded and real-time systems › real-time scheduling
probabilistic timing analysis |
0.4 | 1 | 2019 | Work-in-Progress: Probabilistic System-Wide DVFS for Real-Time Embedded Systems · RTSS 2019 |
Embedded and real-time systems › worst-case execution time analysis
probabilistic worst-case execution time |
0.4 | 1 | 2019 | Work-in-Progress: Probabilistic System-Wide DVFS for Real-Time Embedded Systems · RTSS 2019 |
Parallel and multicore computing › task scheduling
DAG scheduling |
0.3 | 1 | 2018 | Scheduling Multi-periodic Mixed-Criticality DAGs on Multi-core Architectures · RTSS 2018 |
Embedded and real-time systems › real-time scheduling
multiprocessor scheduling |
0.3 | 1 | 2018 | Scheduling Multi-periodic Mixed-Criticality DAGs on Multi-core Architectures · RTSS 2018 |
Processor architecture and microarchitecture
chip multiprocessor |
0.1 | 1 | 2021 | Generalized Mixed-Criticality Static Scheduling for Periodic Directed Acyclic Graphs on Multi-Core Processors · IEEE Trans. Computers 2021 |
Energy-efficient computing
power management |
0.1 | 1 | 2019 | Work-in-Progress: Probabilistic System-Wide DVFS for Real-Time Embedded Systems · RTSS 2019 |
Embedded and real-time systems
real-time embedded systems |
0.1 | 1 | 2019 | Work-in-Progress: Probabilistic System-Wide DVFS for Real-Time Embedded Systems · RTSS 2019 |
Embedded and real-time systems › critical systems
safety-critical systems |
0.1 | 1 | 2018 | Scheduling Multi-periodic Mixed-Criticality DAGs on Multi-core Architectures · RTSS 2018 |
Methods — techniques the papers use, named apart from their topics
meta-heuristic · 0.8G-LLF · 0.5G-EDZL · 0.5G-EDF · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | The Last-Level-Cache Interference in Guest Performance: a Case-Study with Zephyr OSabstractEmbedded systems are increasingly relying on virtual machines (VMs) to ensure portability and composability of services. To achieve high-performance and resources' isolation, the VM can be mapped to a dedicated core. In shared-memory multi/many cores architectures, the last level cache (LLC) is shared among cores. The state-of-the-art shows that interference on LLC can be a bottleneck for VM's performance. Such interference can depend on several factors, including the design of the applications, guest and host OSes, the hypervisor, and the architecture. Therefore, it is expected that studies analyze in-depth each of these factors. The goal of this work is focusing on the interference that cannot be mitigated by cache isolation techniques supported by the hypervisor, for instance, those caused by host OS applications. Such interference is unpredictable and can jeopardize the performance of the guest. The contribution is a new perspective about how cache interference affects the latency of the guest application and guest OS, crossing different performance metrics in comprehensive plots. We run our experiments on Arm Cortex-A53 processor, and, as guest OS, we employ the state-of-the-art Zephyr OS. Thus, a side contribution is to show Zephyr performance facing cache interference. Our results show that interference on LLC can affect in up to +8 × to slow down the guest application and up to +2.8 ×the subset of kernel functions which are involved for the application execution. Results also show that the guest is mostly affected when its data can fit on the LLC: after this point, the LLC saturation occurs and the host interference becomes insignificant from a guest perspective. Marcelo Ruaro, Hadrien Barral, Matteo Bertolino, Rodrigo Cataldo, Roberto Medina 0001, Mohamed Karaoui, Etienne Borde |
DSD | 5 |
| 2021 | Generalized Mixed-Criticality Static Scheduling for Periodic Directed Acyclic Graphs on Multi-Core ProcessorsabstractIn safety-critical systems many software components of different criticalities or assurance levels need to interact in a timely manner to keep the system and environment safe. Nowadays, these systems are challenged by technological progress resulting in rapid increases in both software complexity and processing demands. Efficiently designing safety-critical systems subject to stringent timing requirements is therefore a challenge and a necessity. In this article, we consider the mixed-criticality execution model and homogeneous multi-core processors. We begin by defining a task model incorporating mixed-criticality, real-time and precedence constraints in the form of directed acyclic graphs. A meta-heuristic to solve the scheduling problem of this task model is then defined and proved to respect deadlines, even when the system needs to give more processing power to the most critical tasks. The state-of-the-art techniques capable of scheduling a similar task model have only been developed for dual-criticality systems. Conversely, the meta-heuristic we propose has been generalized to support an arbitrary number of criticality levels. We instantiated our meta-heuristic adopting scheduling algorithms such as G-EDF, G-LLF, or G-EDZL for each level of criticality. The experiments show excellent results in terms of acceptance ratio and number of preemptions. Roberto Medina 0001, Etienne Borde, Laurent Pautet |
IEEE Trans. Computers | 1 |
| 2019 | Work-in-Progress: Probabilistic System-Wide DVFS for Real-Time Embedded SystemsabstractNowadays, real-time embedded systems are facing concerns like power consumption and increased functionalities demand. Approaches based on Dynamic Voltage and Frequency Scaling (DVFS) reduce the energy consumed by processors while guaranteeing real-time constraints. In this paper, we present short-comings on existing models reducing energy consumption. Our experimental results clearly show that the execution time of tasks is not exclusively proportional to the processor speed. Thus, we believe that DVFS techniques could also be applied to other components like buses and memory. We discuss the applicability of a probabilistic Worst Case Execution Time (WCET) combined with DVFS techniques, and argue that by adopting a probabilistic frequency-aware model, we can (i) capture more detailed behaviors of tasks w.r.t. hardware frequencies and (ii) apply DVFS techniques to gain in energy consumption. Roberto Medina 0001, Liliana Cucu-Grosjean |
RTSS | 1 |
| 2018 | Availability enhancement and analysis for mixed-criticality systems on multi-coreabstractIn the critical systems domain, Mixed Criticality Systems (MCS) improve considerably the usage of computation resources by running tasks with different levels of criticality on multi-core processors. To ensure the safety of MCS, services provided by low criticality tasks are degraded or stopped whenever high criticality tasks need more computation time than initially credited. The evaluation of this degradation is hardly considered in the literature although low criticality services are of prime importance for the quality of service (QoS) of critical systems. In this paper, we propose a method to evaluate the availability of low criticality services, i.e. how often these services are delivered in MCS. We also propose a task model that improves this availability, demonstrated thanks to our evaluation method on an illustrative example of MCS. Roberto Medina 0001, Etienne Borde, Laurent Pautet |
DATE | 1 |
| 2018 | Scheduling Multi-periodic Mixed-Criticality DAGs on Multi-core ArchitecturesabstractThanks to Mixed-Criticality (MC) scheduling, high and low-criticality tasks can share the same execution platform, improving considerably the usage of computation resources. Even if the execution platform is shared with low-criticality tasks, deadlines of high-criticality tasks must be respected. This is usually enforced thanks to operational modes of the system: if necessary, a high-criticality execution mode allocates more time to high-criticality tasks at the expense of low-criticality tasks' execution. Nonetheless, most MC scheduling policies in the literature have only considered independent task sets. For safety-critical real-time systems, this is a strong limitation: models used to describe reactive safety-critical software often consider dependencies among tasks or jobs. In this paper, we define a meta-heuristic to schedule multiprocessor systems composed of multi-periodic Directed Acyclic Graphs of MC tasks. This meta-heuristic computes the scheduling of the system in the high-criticality mode first. The computation of the low-criticality scheduling respects a condition on high-criticality tasks' jobs, ensuring that high-criticality tasks never miss their deadlines. An efficient implementation of this meta-heuristic is presented. In high-criticality mode, high-criticality tasks are scheduled as late as possible. Then two global scheduling tables are produced, one per criticality mode. Experimental results demonstrate our method outperforms approaches of the literature in terms of acceptance rate for randomly generated systems. Roberto Medina 0001, Etienne Borde, Laurent Pautet |
RTSS | 1 |