We present a practical flow that automates the process of analyzing noise failures and determining and implementing the most appropriate design fixes in high performance designs. For each noise problem, the flow implicitly identifies the most sensitive relevant electrical parameter(s) which it then maps to a physical solution that minimizes design perturbation. Integrated with standard physical synthesis, it was used extensively in a high volume 90 nm multi-GHz microprocessor project.

Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime. Interconnect-capacitance extraction is complicated by the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-/spl kappa/ polymeric dielectrics used in high-performance ICs. A CAD procedure using the novel floating random-walk extractor QuickCAP is presented. Our procedure is efficient enough to extract a substantial amount of a chip's 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based on effective conductor geometry or on a finite-sized conductor library but rather on the entire 3-D layout, accounting for actual local variations in conductor separations and shapes. We then apply our procedure to an experimental circuit vehicle implemented in AlGaAs-GaAs heterojunction bipolar transistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test-capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed all interconnects in an adder carry-chain oscillator using our procedure. Predicted propagation delays were generally within 3% of measurement.

A digital voltage-controlled oscillator (VCO) is described which uses frequency multiplication and division to achieve very wide bandwidth. The VCO uses current-mode logic and does not require reactive elements such as inductors, capacitors or varactors. A novel, fully symmetric exclusive-OR (XOR) circuit was developed which uses product pairs and emitter-coupled logic. To achieve the highest performance possible, the critical path is symmetric and special physical design techniques were developed to promote matched-capacitance. The maximum measured frequency was 13.66 GHz. The chip occupies 1.9 mm/spl times/1.6 mm and dissipates 2.45 W at a supply voltage of -6.0 V. With a measured frequency range from 1.25 to 13.66 GHz, this circuit has the widest bandwidth reported in the literature for any VCO, digital or analog.

This paper examines the design of a 32-b GaAs Fast RISC microprocessor (F-RISC/I). F-RISC/I is a single chip GaAs Heterojunction MESFET (HMESFET) processor targeted for implementation on a multichip module (MCM) together with cache memories. The CPU architecture, circuit design. Implementation, and testing are optimized for a seven-stage instruction pipeline implemented with GaAs super-buffered FET logic (SBFL). We have been able to verify novel GaAs SBFL standard cells and compare measured CPU performance with performance estimates based on circuit and device models. The prototype 32-b microprocessor has been implemented using an automated standard cell approach because of time constraints and fabricated using an experimental process by Rockwell International. The CPU chip integrates 92340 transistors on a 7/spl times/7 mm/sup 2/ die and dissipates 6.13 W at 180 MHz. Test results from a prototype fabrication run have demonstrated the operation of the ALU, the program counter, and the register file with delays below 6, 5, and 3.4 ns, respectively. The successful modeling and verification indicate that a 0.5 /spl mu/m HMESFET implementation of F-RISC/I could achieve a peak performance of 350 MHz. The wiring delays account for 42% of the critical path delay.

A ready supply of high quality Known Good Die (KGD) is essential for obtaining acceptable Multi-Chip Module (MCM) yields and reducing costs. Unfortunately, the testers needed for testing and screening VLSI chips to supply high quality KGD are quite expensive, especially for high speed or high pin count ICs. In addition, there are issues connected with testing accuracy-the tester environment may limit performance testing because of interconnect length and capacitance, and with burn-in-which may require temporary packaging of die. Building special test equipment is only cost effective if production volumes are large. Hence, a low cost alternative for at-speed testing that yields high quality die is needed to drive down the cost of low volume or prototype MCMs. This paper describes a double-blind experiment devised to prove the viability of a KGD methodology based upon wafer level test-using embedded performance testing circuits-and wafer level burn-in.

The design of an advanced high density thin film multichip module (MCM) for a 1-ns cycle time Fast Reduced Instruction Set Computer (F-RISC/G) is described. The processor has been implemented with GaAs/AlGaAs heterojunction bipolar transistor (HBT) technology from Rockwell International. The F-RISC/G package pushes the state of the art to satisfy electrical, thermal and thermomechanical constraints to take advantage of this high speed circuit technology. A unique approach is developed to link the electrical and thermomechanical design environments using a common database.>

Multichip module (MCM) technology is attracting attention from designers who need high-speed interchip connections and a reliable package for their circuit applications. This technology is being applied to realize a 1-ns cycle time 32-bit RISC processor, using 50 GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology and triple-level full-differential current mode logic (CML), at Rensselaer. The processor is partitioned into multiple chips due to the high power consumption and low integration level of the technology. There are several key challenges associated with this module. It has to provide high-bandwidth (/spl les/10 GHz) and high-density (/spl les/40 /spl mu/m pitch) interconnect, and dissipate nearly 250 W of power. Maximum heat flux on the MCM surface is 2.0/spl times/10/sup 5/ W/m/sup 2/. Poor heat conduction ability of GaAs chips make it tough to dissipate this hear. A methodology is developed to design a thermally stable module using a multilayer substrate with parylene as a low dielectric constant insulator, and fine pitch copper for high bandwidth lines. The design of the MCM and the thermal simulation results are presented.>

A standard cell library for implementing Rensselaer's fast reduced instruction set computer (F-RISC/G) project with Rockwell's AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology is presented. The processor is targeted at an instruction cycle time of 1.0 ns. Differential current mode logic (CML) is used, and unloaded gate delays are 15-20 ps.>

F-RISC/I is a monolithic GaAs microprocessor with a seven stage pipeline implemented with SBFL standard cells. It is targeted at a clock rate of 400 MHz with a CPI of 1.45. The impacts of GaAs technology on system architecture, CPU architecture, circuit level optimization, implementation, performance, and testing of F-RISC/I are discussed. The GaAs technology environment is investigated and compared to that of Si.>