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Joel McGrath

dblp:15/5006 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 77% Integrated circuit design · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › system-level design
chip-package co-design		 0.112006
The importance of adopting a package-aware chip design flow · DAC 2006
Electronic design automation
physical design		 0.112006
The importance of adopting a package-aware chip design flow · DAC 2006
Integrated circuit design
digital circuit design		 0.012006
The importance of adopting a package-aware chip design flow · DAC 2006
Integrated circuit design
interconnect		 0.012006
The importance of adopting a package-aware chip design flow · DAC 2006

Methods — techniques the papers use, named apart from their topics

simultaneous interconnect synthesis · 0.1
YearPublicationVenuePosition
2006 The importance of adopting a package-aware chip design flow
abstract
In this paper, we talk about the short- and long-term implications of ignoring the relationship between the chip, package and PCB during I/O planning and how these issues will manifest themselves as we move toward 65 and 45nm technology.It also introduces a whole new approach to chip/package I/O planning and optimization. This new approach simultaneously synthesizes the entire interconnect from the I/O driver to the package ball and establishes an interconnect plan that is optimized for both chip and package.
Kaushik Sheth, Egino Sarto, Joel McGrath
 DAC3