Silicon photonic technology offers seamless integration of multiple chips with high bandwidth density and lower energy-per-bit consumption compared to electrical interconnects. The topology of a photonic interconnect impacts both its performance and laser power requirements. The point-to-point (P2P) topology offers arbitration-free connectivity with low energy-per-bit consumption, but suffers from low node-to-node bandwidth. Topologies with channel-sharing improve inter-node bandwidth but incur higher laser power consumption in addition to the performance costs associated with arbitration and contention.

Silicon photonics is a promising technology to scale offchip bandwidth in a power-efficient manner. Given equivalent bandwidth, the flexibility of switched networks often leads to the assumption that they deliver greater performance than point-to-point networks on message passing applications with low-radix traffic patterns. However, when optical losses are considered and total optical power is constrained, this assumption no longer holds. In this paper we present a power constrained method for designing photonic interconnects that uses the power characteristics and limits of optical switches, waveguide crossings, inter-layer couplers and waveguides. We apply this method to design three switched network topologies for a multi-chip system. Using synthetic and HPC benchmark-derived message patterns, we simulated the three switched networks and a WDM point-to-point network. We show that switched networks outperform point-to-point networks only when the optical losses of switches and inter-layer couplers losses are each 0.75 dB or lower; achieving this would require a major breakthrough in device development. We then show that this result extends to any switched network with similarly complex topology, through simulations of an idealized "perfect" network that supports 90% of the peak bandwidth under all traffic patterns. We conclude that given a fixed amount of input optical power, under realistic device assumptions, a point-to-point network has the best performance and energy characteristics.

Scaling trends of logic, memories, and interconnect networks lead towards dense many-core chips. Unfortunately, process yields and reticle sizes limit the scalability of large single-chip systems. Multi-chip systems break free of these areal limits, but in turn require enormous chip-to-chip bandwidth. The "macrochip" concept presented here integrates multiple many-core processor chips in a single package with silicon-photonic interconnects. This design enables a multi-chip system to approach the performance of a single large die.

We present a computing microsystem that uniquely leverages the bandwidth, density, and latency advantages of silicon photonic interconnect to enable highly compact supercomputer-scale systems. We describe and justify single-node and multinode systems interconnected with wavelength-routed optical links, quantify their benefits vis-a-vis electrically connected systems, analyze the constituent optical component and system requirements, and provide an overview of the critical technologies needed to fulfill this system vision. This vision calls for more than a hundredfold reduction in energy to communicate an optical bit of information. We explore the power dissipation of a photonic link, suggest a roadmap to lower the energy-per-bit of silicon photonic interconnects, and identify the challenges that will be faced by device and circuit designers towards this goal.

This paper describes a performance monitoring system, Monit, developed for performance evaluation of parallel systems. Monit uses trace files that are generated during the execution of parallel programs. Monit analyzes these trace files and produces time-oriented graphs of resource usage and system queues. Users interactively select the displayed items, resolution, and time intervals of interest. The current implementation of Monit is for SUN-3 workstation, but the program is easily adaptable to other devices.

Abstract With the aid of the EM (encoding machine) compiler tool kit, a preliminary version of a scalar C compiler was implemented on the Cyber 205 in a relatively short period of time. This C compiler emphasizes functionality more than efficiency. Several benchmark programs were used to measure the performance and to compare it with an equivalent C compiler for the VAX/UNIX system. In order to make it a production‐quality C compiler, further enhancements will be necessary. This paper presents some motivating factors, implementation details, and proposes further work on developing the Cyber 205 C compiler.

Several interconnection structures for a distributed multimicrocomputer message-passing system are compared on the basis of cost and performance. Among the structures analyzed are buses, double rings, D-dimensional toroids, trees, cube-connected cycles, and chordal rings. Network cost is defined in terms of the number of network nodes and the unit cost of communication links and their associated connections. Simple asymptotic performance bounds are derived based on the bottleneck analysis of a queueing network. In contrast to the usual assumption of uniform message routing, the technique permits the introduction of a reference locality notion to the message routing behavior of network nodes. Finally, the cost, performance, and performance/cost functions are examined as the number of network nodes becomes very large.

A system model is a tool used to predict system performance under changing conditions. There are two widely used modeling techniques: one based on discrete event simulation and one based on queuing theory models. Because queueing theory models are so much cheaper to implement and use, as compared to simulation models, there is growing interest in them. Users are developing and using queuing theory models to project system performance, project capacity, analyze bottlenecks and configure systems.

Abstract The job‐scheduling function in a multiprogramming computer system plays a key role in the achievement of the performance goals for the system. It is possible and convenient to partition this scheduling function into a priority assignment function and resource assignment function. Implementation of a general purpose resource assignment module permits a large family of scheduling strategies to be implemented via different priority calculation schemes. The implications of this partitioning of the scheduling function are studied by use of a simulation model. A system embodying this approach to job scheduling is discussed as an application of the approach to other types of systems.

No abstract available.

ABST~tACT.In multiprogramming computer systems, the scheduling strategy used to select tasks to be activated is an important factor in the achievement of the performance goals of the system.One form of analysm of scheduling algorithms represents the system as an abstract model of computation and then formally analyzes the algorithms operating in the context of the model.This paper presents an abstract system model which consists of several identical and independent task processors and a memory of arbitrary size Tasks are represented by processing-time and memory requirements which must be met by the model.Worst-case performance bounds are derived for sever al simple scheduling algortthms.A new heuristic algorithm, which uses a look-ahead strategy, is introduced This algorithm is shown to be better in many cases than the simpler algorithms when the worst-case performance bounds are compared.

The MESA subsystem provides a wide variety of services to remotely located users of the computing facilities of the Purdue University Computing Center. This paper presents the preliminary steps of an in-depth study into the behavior of MESA. The study uses a software data-gathering facility to analyze the usage and queueing aspects of this behavior and to provide values for parameters used by two models of the subsystem. These models, a network-of-queues model and a simulation model, are designed to project subsystem behavior in different operating environments. The paper includes a number of tables and figures which highlight the results, so far, of the study.

This paper presents a description and analysis of a task scheduling algorithm which is applicable to third generation computer systems. The analysis is carried out using a model of a computer system having several identical task processors and a fixed amount of memory. The algorithm schedules tasks having different processor-time and memory requirements. The goal of the algorithm is to produce a task schedule which is near optimal in terms of the time required to process all of the tasks. An upper bound on the length of this schedule is the result of deterministic analysis of the algorithm. Computer simulations demonstrate the applicability of the algorithm in actual systems, even when some of the basic assumptions are violated.