In this article, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric FinFETs (Fe-FinFETs) for asymmetric nonperiodic input signals. We use the multidomain Preisach Model to capture the saturated$P$–$E $loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history-dependent minor loop paths in the$P$–$E $by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an RC circuit-based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of the 7-nm FinFET.

Reliability of inverters in electric vehicles (EV) is one of the limiting factors for increased penetration of EVs. The power semiconductor devices (PSDs) are more prone to failure than the other components in EV inverters, due to frequent thermal cycling. For reliability oriented design of an EV inverter, it is essential to study the impact of different EV operational conditions on PSD lifetime. In this paper, an integrated model based study of lifetime of PSDs in EV inverter is presented. The study is carried out for light weight passenger electric car with single speed transmission (SST). The study assimilates the effect of various operational factors on the lifetime of PSD. These factors include transient driving cycles, transmission gear ratio value and extent of energy recuperation. It is found that the lifetime of PSD is severely affected due to aggressive driving patterns, random gear ratio selection of SST and high energy recuperation. The detailed simulation results and their analysis are included in the paper.