Implementation of low energy, low latency transmission line interconnects on a network-on-chip presents the circuit designer with a variety of structural design choices. This work presents a study of the comparative effects of changing the wire geometries on the latency, energy dissipated, area, and noise properties of the transmission lines. These results will aid the engineer in the design and performance analysis of the global interconnect and foster a quantitative understanding of the wave signaling properties in the RLC regime.

We present an efficient and scalable framework for the generation of guaranteed passive compact dynamical models for multiport structures. The proposed algorithm enforces passivity using frequency independent linear matrix inequalities, as opposed to the existing optimization based algorithms which enforce passivity using computationally expensive frequency dependent constraints. We have tested our algorithm for various multiport structures. An excellent match between the given samples and our passive model was achieved.

We present a high-frequency impedance extraction method for horizontal interconnects as needed in 3-D integrated circuits (ICs), where the horizontal interconnects are sandwiched between substrate layers of possibly different electromagnetic parameters. In particular, for the first time, we develop an extension of the discrete complex images method based on a 2D, or alternatively, 3D magneto-quasi-static (MQS) vector potential Green's functions to extract analytical solutions to the series impedance (resistance and inductance) matrix elements for wire filaments. We then follow standard methods to extract the port impedance. Using the 2D approach, the series impedance per unit length of horizontal wire loops is obtained, which shows excellent accuracy (<; 1% error to Maxwell SV) and significantly improved computational cost (two orders faster than Maxwell SV). Using our 3D approach and combining the series impedance matrix from the MQS extraction engine with the capacitance matrix from an electrostatic extraction engine, we produce an electro-magneto-quasi-static impedance matrix extraction engine, which is used to extract the input impedance of a spiral inductor. In the frequency range spanning near dc to a high frequency cutoff given by four times the frequency of the maximum in the quality factor, we show that our results agree to within less than 5% and 11% deviation to the full-wave simulator HFSS, for the self and mutual loop impedance, respectively. The CPU time using our approach is 18-25× faster than HFSS. These results provide a reasonable foundation for circuit block-level impedance extraction for interconnects and inductors in 3-D integrated systems.

We present an efficient and highly accurate approach to high-frequency impedance extraction for VLSI interconnects and intentional on-chip inductors. The approach is based on a three-dimensional (3D) loop formalism that uses discrete complex images approximations applied to a quasi-magnetostatic treatment of the vector potential, resulting in closed-form expressions for the impedance matrix of current filaments in the presence of a multi-layer substrate. Populating the impedance (Z) matrix for 3D configurations of finite transverse dimensions (including non-Manhattan wires and inductors) is computationally inexpensive, and includes substrate eddy current effects that become quantitatively important in the frequency regime beyond 20 GHz which is imminent at the 45 nm technology node onwards. The accuracy, as exemplified by the magnitude of inductor impedance |Z|, is within 5% of a full-wave electromagnetic field solver for frequencies up to 100 GHz, with an order of magnitude lower computation cost. The proposed method represents a core technology for incorporation into system level extraction of analog systems consisting of multiple inductors and nearby interconnects, for CMOS on-chip circuits in the nanometer era.

In the above titled paper (ibid., vol. 28, no. 7, pp. 1047-1060, Jul. 09), there is an error in equation (17) and equation (15) should be modified. The corrections are presented here.

We propose an efficient method to accurately compute the frequency-dependent impedance of VLSI interconnects in the presence of multilayer conductive substrates. The resulting accuracy (errors less than 3%) and CPU time reduction (more than an order of magnitude) emerge from three different ingredients: a 2-D Green's function approach with the correct quasi-static limit, a modified discrete complex images approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the short distances that are relevant to VLSI interconnects. This approach permits the evaluation of the self-impedance and mutual-impedance of multi-conductor current loops, including substrate effects, in terms of easily computable analytical expressions that involve their relative separations and the electromagnetic parameters of the multilayer substrate.

We propose a computationally efficient method to calculate, with high accuracy, the mutual impedance between two wires in the presence of multilayer substrates, as needed for high frequency CAD applications. The resulting accuracy (errors smaller than 2%) and CPU time reduction (factors of seven) emerge from three different ingredients: a two dimensional Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a novel discrete dipole approximation to evaluate the magnetic vector potential. This approach permits the evaluation of the mutual impedance between two loops in terms of easily computable analytical expressions that involve the relative separations and the electromagnetic parameters of the multi-layer substrate. The results are valid for long wires, for any separation, and for frequencies up to 100 GHz.

International audience

We present closed form analytical expressions for the mutual inductance between intentional inductors. The formalism is applicable for border to border separations that are longer than 0(1/10) of the inductor radius. The results are exact in leading order multi-pole expansion for the magnetic field generated by a superposition of current loops, acting on an external device. The derived expressions are simple analytical formulae. We present examples for the closed form expressions for a number of configurations used by RF designers including non Manhattan devices. The computational complexity of the result is linear with the number of segments. Detailed comparisons against standard methods are included, the CPU gains are two orders of magnitude. The formulae are useful for quick estimation of magnetic noise parameters during RF circuit layout synthesis

The notion of design for manufacturability is blurring the separation between the tasks of design and manufacture. In the era of nano-technologies, the description of the design rules has retreated back to an early stage form of many conditional cases and even an art. Thus, it is important to set the metrics for the manufacturability. However, who is going to be held accountable for the final outcomes? Should the designer, the EDA developer, the manufacture engineer, or a new breed of experts take the lead to tackle the problem?

This paper examines the controversy between two approaches to inductance extraction: loop versus partial treatments for integrated circuit applications. We advocate the first one, and explicitly show that the alternative demands monopole-like magnetic configurations as well as dense inductance matrices. We argue that the uncertainties in the loop inductance treatment associated with possibly unknown return paths are in fact negligible for frequencies where inductance effects are important. Within the loop formulation, we develop an efficient way of computing mutual inductances between loops in terms of the field generated by a magnetic dipole. We derive easily computable analytical formulas. On numerical simulations, this dipole approximation (DA) shows good accuracy when compared to FastHenry, down to distances smaller than 30 /spl mu/m for 90-nm lithography. The DA leads naturally to selection rules for discarding the coupling for certain geometrical configurations, an experimentally verifiable prediction.

The present work is centered in the controversy between two approaches to inductance extraction: loop vs. partial treatments for IC applications. We advocate for the first one, justifying this claim in terms of representing more realistically the physical situation, as well as having better sparseness properties. We argue that the drawbacks of loop inductance treatment are small for frequencies above 1 GHz. Within the loop inductance formulation, we develop an efficient way of calculating mutual inductances between loops in terms of the field generated by a magnetic dipole. On numerical simulations, the dipole approximation shows good accuracy when compared to FastHenry, down to distances of 30μ for 0.13μ processes. The dipole approximation leads naturally to selection rules for discarding certain couplings that can be experimentally verified.

With the onset of gigahertz frequencies on clocked digital systems, inductance effects become significant. We investigate appropriate regimes where signal propagation on an IC can be characterized as resulting from transmission line (TL) behavior. The signals propagate at a speed in the proximity of the speed of light in the medium. Our starting points are exact solutions in the time domain to the TL equations. A methodology to evaluate the feasible domains of physical and electrical variables that permit TL propagation is given. We develop fast and accurate computational methods for inductance and capacitance calculations. A general expression of the time delay in the presence of finite rise time and finite load capacitance for TL propagation is derived. We analyze a clock-synthesis method based on sandwiched balanced H-trees consistent with TL propagation. We find the feasible physical domains by solving iteratively two nonlinear equations in a space spanned by two continuous variables, with four parameters. To further assert its applicability we remove common assumptions such as the constancy of the electromagnetic parameters, zero rise time, and load capacitance. The spectrum of configurations is satisfactory at 130 nm and scales well into the 45-nm generation.

We investigate appropriate regimes for transmission line propaga-tion of signals on digital integrated circuits. We start from exact solutions to the transmission line equations proposed by Davis and Meindl. We make appropriate modifications due to finite rise time. They affect the delay calculation and hypothesis pertaining the con-stancy of the electromagnetic parameters. We study these effects in detail. To find the domain of physical variables where transmission line behavior is feasible, we pose the problem as a nonlinear mini-mization problem in a space spanned by two continuous variables, with four parameters. From the resulting solutions and employing monotonicity properties of the functional we extract regimes of va-lidity. These regimes of validity happen to be commensurate with what is reachable and doable with todays leading technologies. We complete this study with a qualitative analysis of driver insertion in the presence of transmission lines. The resulting configurations are suitable for the development of an improved clock design dis-cipline. 1.

We present a two-dimensional layout compactor with octagonal geometry.We discuss layout optimization algorithms used within a topological framework.We present the results of comparing the compactor against a standard set of benchmarks.This version of the compactor uses an iterative greedy layout optimization algorithm with wire minimization and produces leafcells more compact than others published.

An effective approach to two-dimensional compaction of VLSI circuit layouts is discussed. Active devices are described in terms of circular primitives called bubbles. The wires are treated topologically in that no geometric representation is used for them during compaction. This avoids expensive geometrical manipulations of the wires. Cells are compacted by moving bubbles one at a time along design rule preserving paths so as to minimize a cost function directly related to the size of the cell. Geometrical realizations of the wires are reconstructed at the end of the compaction process. The resulting routing has minimum wire length for each wire.>