We consider the problem of adding the partial products in the combinational decimal multiplier presented by Lang and Nannarelli. In the original paper this addition is done with a tree of decimal carry-save adders. In this paper, we treat the problem using the multi-operand decimal addition previously published by Dadda, where the sum of each column of the partial product array is obtained first in binary form and then converted to decimal. The multiplication, using a 90 nm CMOS technology, in this modified scheme takes 2.51 ns, while in the original scheme it takes 2.65 ns. The area of the two schemes is roughly the same.

This paper introduces a hardware architecture for high speed network processors, focusing on support for quality of service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support quality of service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.

Decimal arithmetic has been revived in recent years due to the large amount of data in commercial applications. We consider the problem of multioperand parallel decimal addition with an approach that uses binary arithmetic, suggested by the adoption of binary-coded decimal (BCD) numbers. This involves corrections in order to obtain the BCD result or a binary-to-decimal (BD) conversion. We adopt the latter approach, which is particularly efficient for a large number of addends. Conversion requires a relatively small area and can afford fast operation. The BD conversion moreover allows an easy alignment of the sums of adjacent columns. We treat the design of BCD digit adders using fast carry-free adders and the conversion problem through a known parallel scheme using elementary conversion cells. Spreadsheets have been developed for adding several BCD digits and for simulating the BD conversion as a design tool.

Hash functions are an important cryptographic primitive. They are used to obtain a fixed-size fingerprint, or hash value, of an arbitrary long message. We focus particularly on the class of dedicated hash functions, whose general construction is presented; the peculiar arrangement of sequential and combinational units makes the application of pipelining techniques to these constructions not trivial. We formalize an optimization technique called quasi-pipelining, whose goal is to optimize the critical path and thus to increase the clock frequency in dedicated hardware implementations. The SHA-2 algorithm has been previously examined by Dadda et al, with specific versions of quasi-pipelining; a full generalization of the technique is presented, along with application to the SHA-1 algorithm. Quasi-pipelining could be as well applied to future hashing algorithms, provided they are designed along the same lines as those of the SHA family.

After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.

An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13um technology.

Microcontrollers for embedded computer applications require a library of dedicated macrocells for specific applications. Arithmetic and basic digital signal processor (DSP) computations may be too inefficient when computed by software on the core central processing unit (CPU) of the microcontroller. Here the architecture of a VLSI macrocell is defined and developed for the ST9 microcontroller (8 bits), for the computation of the inner (scalar) product of two vectors of integer numbers based on the multiply/accumulate algorithm. The arithmetic core of the macrocell is an integer pipeline. This macrocell fully interfaces to the ST9 environment and is optimized so as to achieve the maximum performances compatible with the bandwidth of the bus of ST9 and the minimum consumption of silicon area. The macrocell Is implemented in CMOSM5H technology (0.7 /spl mu/ channel width) and its performances, measured in terms of silicon area and throughput, are evaluated.

The FERMI is a data acquisition system for calorimetry experiments in high energy physics at the LHC, CERN. The system contains a large number of acquisition channels, with a precision of 16 bits and a sampling rate of 40 MHz. A large part of the information driven by the channels is processed locally, to reduce the amount of data. This requires to cluster several channels by adding them. The paper presents the design of a fast, low cost adder chip, based on the implementation of column compression techniques for the computation of integer addition. Since the system is operating in a radiation-hard environment, fault tolerance (namely fault detection) is implemented by means of arithmetic codes.

A well-known scheme for obtaining high throughput adders is a pipeline in which each stage contains an array of half-adders performing a carry-save addition. This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder. Such schemes offer a considerable savings of components while preserving high throughput. These schemes can be generalized by using (p,q) parallel counters to obtain pipelined adders for more than two numbers.

The paper presents a study on the introduction of pipelining in parallel VLSI multipliers, built according to the column compression (CC) design techniques. A number of CC multiplier schemes have been proposed in the literature, aimed at reducing the number of stages of adders necessary to compute a multiplication. More recently CC multiplier schemes aimed at optimising the required silicon area, the regularity and the locality of the interconnections among the adders, have been proposed. The paper affords the introduction of pipelining in these last structures and compares the obtained results with existing structures, in terms of required number of components and operation frequency.

A dedicated digital signal processor has been designed as part of a fully digital front-end for calorimetric detectors developed for experiments in high-energy particle physics to be carried out at CERN with the Large Hadron Collider. Its function is to evaluate the collision energy by analyzing the 16-bits samples (at 67 Msamples per second) contained in a time window through convolutions with 10-bits coefficients. In order to improve the time and amplitude accuracy of the evaluated pulse maximum, we adopted a scheme composed of three inner-product units followed by a sorting circuit which identifies the maximum, the minimum and the median value among the three inner-product outputs. Due to the massively radioactive environment in which the calorimeter operates, the fault tolerance issues have been particularly taken into account to provide both concurrent error detection through residue arithmetic and graceful degradation.>

A scheme for a convolver design, called a multiparallel convolver, that is based on concurrent processing of p adjacent samples that are input simultaneously to the p-parallel convolver is presented. The scheme uses p units, each of which receives the input samples and produces one convolution every p samples; these are called p-phase subconvolvers. The detailed design of the p-phase subconvolvers and of the whole p-parallel convolver is presented and discussed. The scheme can be used for both the bit-parallel and the bit-serial input presentation of each sample. The input sample rate of the p-parallel convolver is p times the sample rate of a standard (1-parallel) convolver implemented using the same integration technology. The number of components required by a p-parallel convolver is approximately p times the number of components required by a standard convolver.>

It is shown that previously proposed bit-serial convolver schemes (with weights in parallel form), working with zero separation between samples, can be transformed into byte-serial input schemes with a comparable clock rate, thus affording an increase in sampling rate equal to the number of bits in each byte. This is achieved by adopting a modified carry save circuit. The proposed schemes are based on a modified version of serial-parallel multipliers and on the use of pre-computed multiples of the weights. The case of 2-bit bytes is fully developed. It is shown that the use of samples represented in a biased binary number system leads to schemes that are only slightly more complex than the corresponding bit-serial schemes. The bit rate is determined by the delays of a full adder and a flip-flop. The schemes are composed by a number of bit-slices and appear to be easily partitionable in identical cascaded modules suitable for a fault tolerant architecture and a WSI implementation.>

A general theory of serial-input-serial-output polyphase convolvers based on modules (phases) producing one convolved output every p samples is presented. Methods are presented for designing these convolvers for arbitrarily assigned weights, sample lengths, and number of convolution terms, under the assumption of zero, or assigned, interval between successive samples, minimum number of phases, and minimum intervals between successive convolved output from each phase. Two types of solution are shown, the first based on the use of distinct serial-parallel multipliers and the second on multipliers partially shared among successive convolution terms. A structure based on bit-slices is presented, permitting a convolver with assigned parameters to be designed from a stack of slices.>

The author shows that a multiplier already proposed by T. Rhyne and N.R. Strader (see ibid., vol.C-35, p.896-901 (1986)) for unsigned numbers can be used for two's complement numbers as well, provided only that the content of the input registers is held constant, after the introduction of the operand's sign bits, for a number of clock periods equal to the operand's length. The result is derived by the properties of sign-extended two's complement numbers. The known multiplier includes a linear array of (5, 3) parallel counters and a set of three static registers for the internal carriers. It is shown that a logically equivalent multiplier can be built using two linear arrays of full adders and two carry registers. In a faster circuit, an additional carry register is required.>

A novel convolver is presented in which both samples and results are in serial form, while coefficients are stored in internal registers. The convolver is composed of an array of multiplier-accumulator subunits which operate in a carry-save, serial/parallel mode. The sample bits are broadcast to all subunits, each one executing the multiplication with the stored coefficient and accumulating the product with the result received from the preceding unit. The structure can be shown to be decomposable in bit-slices; a stack of slices can be programmed as a convolver for prescribed sample and coefficient bit-length under the control of a configuration register. Faulty slices can be neutralized by variables stored in a second register.>

Schemes for designing multipliers of binary-two's-complement numbers in serial form are considered with the condition of the least possible delay between inputs and output. Such schemes are composed by two parts: the first, the array generator, produces the terms of the multiplier array; the second, the summer, is fed by the array generator and produces the product. Two classes of multipliers are illustrated: the first generating the multiplier array by diagonals and rows, the second by columns. The array generators are composed by shift and/or stack registers and linear arrays of logic gates; the summer is shown to be conveniently built using parallel counters.

The problem of designing squarers for binary number in serial form (with the condition of the least possible delay between input and output) is treated. Several schemes are Illustrated, derived from fast multipliers for binary numbers in serial form, described in a previous paper. It is shown that some of such multipliers offer a considerable saving in components when they are reduced to squarers. Some schemes are illustrated, both for positive and for two's-complement numbers.

The design of fast multipliers for binary numbers represented in serial form is considered according to a general scheme composed by an array generator and a summator. The bits of the product are generated with the least delay with respect to the operators bits. The array generator computes the elements of the multiplier array. The summator computes the sum of the array elements in order to generate the product bits. The array elements can be generated according to two different general schemes: the first computes all the new array elements at each step (arranged on a diagonal and on a row of the multiplier array), the second computes the multiplier array elements column by column, Several schemes of array generators are given and compared, and for each of them a suitable summator using parallel counters is illustrated.

A graphical representation is presented for parallel counters, i.e., multiple input combinatorial modules that count the number of inputs being in a given state (normally logic ONE).

It is shown how circuits for the addition of several serial binary numbers can be obtained as a combination of parallel counters and memory cells. The various schemes belong to one of three different classes, characterized by the way in which carries, produced by parallel counters, are treated. A comparison is made between the various schemes, in terms of speed and complexity.