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Rao R. Tummala

dblp:15/6863 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 3 · 2 first-authorSystems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 98% Energy-efficient computing · 2%
Computer networks
1 paper
Wireless networking · 100%

Topics — the 4 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › packaging
system-in-package
0.012004
Gigabit wireless: system-on-a-package technology · Proc. IEEE 2004
Integrated circuit design › packaging
multichip module
0.011992
Multichip packaging-a tutorial · Proc. IEEE 1992
Integrated circuit design
packaging
0.011992
Multichip packaging-a tutorial · Proc. IEEE 1992
Energy-efficient computing
thermal management
0.011992
Multichip packaging-a tutorial · Proc. IEEE 1992

Methods — techniques the papers use, named apart from their topics

multilayer packaging · 0.1integrated antenna · 0.1baluns · 0.1thin film · 0.0printed wiring · 0.0ceramic · 0.0
YearPublicationVenuePosition
2017 System Scaling With Nanostructured Power and RF Components
abstract
The emergence of smartphones and other smart systems is driving new trends in electronics scaling that goes beyond transistors or active devices, to include all the system components such as packaging substrates, passive components, thermal structures, power sources, and the system interconnections. Current system components are at milliscale, creating a 103to 106scaling gap with the packaging interfaces at microscale, and transistors at nanodimensions. With current microstructured materials, component miniaturization also degrades performance metrics such as efficiency, tolerance or precision, thermal and frequency stability. Nanostructured materials and processes can potentially miniaturize these system components, while simultaneously enhancing the performance. These nanostructured components are assembled close to the active devices, resulting in ultraminiaturized and ultrathin systems with 3-D integration of passives with actives. This paper shows the impact of nanostructured materials toward enhancing the performance and miniaturization of power and radio-frequency (RF) passive components in emerging smart systems. Opportunities for nanostructured materials in improving the power density and efficiency of capacitors and inductors in power-supply modules are reviewed in the first part of the paper. The impact of nanostructured magnetic, dielectric and magneto-dielectric films on emerging RF subsystems is illustrated in the last part of the paper.
Markondeya Raj Pulugurtha, Himani Sharma, Srikrishna Sitaraman, Dibyajat Mishra, Rao R. Tummala
Proc. IEEE5
2004 Gigabit wireless: system-on-a-package technology
abstract
The system-on-a-package (SOP) concept is considered as the solution of future communication modules, where more functionality, better performance, low cost, and more integrity is needed. We demonstrate how SOP technology can address the integration platform for future communication systems, especially gigabit wireless communications. After the introduction of the SOP concept, we introduce the critical design building blocks which are required in a viable SOP technology: integrated passives, embedded RF functions, including high-performance filters and baluns, and integrated antenna technologies. Second, we review how the three-dimensional deployment of core elements, such as baluns, lumped inductors, capacitors, and resistors, as well as IF or low-pass filters, enables RF-SOP module development. We demonstrate how advanced radio architectures, including direct conversion, antenna diversity, and collaborative signal processing, are enabled using the SOP technology format. Various ceramic and organic material based multilayer packaging technologies have been used for building such integrated modules as well as circuit blocks. The critical issues and challenges for developing advanced communication platforms using the SOP approach are discussed.
Rao R. Tummala, Joy Laskar
Proc. IEEE1
1992 Multichip packaging-a tutorial
abstract
Several aspects of the multichip module technology, including its functions, leverages, applications, and markets, are reviewed. All the packaging technologies used in multichip, such as sealing and encapsulation, heat removal, chip level connections, thin film, ceramic, and printed wiring, are discussed. The module corrections and electrical testing used in forming a high-performance or portable system are also discussed.>
Rao R. Tummala
Proc. IEEE1
1991 High Performance Packaged Electronics for the IBM ES9000TM Mainframe
abstract
An 1100 circuit bipolar gate array and a multi-chip high density glass-ceramic module are described. The chip features multiple logic circuit families built using a modular cell approach. Key features include use of a capacitor for faster ECL delays and the introduction of a 200 mV signal swing differential cascode current switch. The module offers a glass ceramic substrate featuring a dielectric constant of 5.2 and a total of 63 layers of metallization. The cooling capability has been increased to 30 W per chip.>
Arnold E. Barish, James P. Eckhardt, Mark D. Mayo, Walter A. Svarczkopf, Santosh P. Gaur, Rao R. Tummala
ICCD6