RF-signal power reflections produced by impedance mismatches remain a critical limitation in high-frequency systems, degrading their operational performance, robustness, and RF-signal integrity. Typical RF-protection mechanisms, such as inter-RF-stage attenuators, isolators$\boldsymbol {/}$circulators, or RF-signal-cancellation loops, often impose penalties in terms of increased in-band insertion-loss levels, size, cost, DC-power consumption, and design complexity. To overcome these challenges, reflectionless or absorptive RF circuits have emerged as an alternative paradigm. They intrinsically absorb undesired stopband$\boldsymbol {/}$non-transmitted RF signals, thereby providing broad-band impedance matching. This overview paper reviews the latest advances on RF reflectionless circuits, covering their fundamental RF design principles and more-recent developments. Beyond the well-established case of RF reflectionless filters illustrated through several state-of-the-art implementations in 3-D and planar technologies, other emerging designs are also addressed. They include reflectionless beyond-transmission-band-flat-group-delay single-ended bandpass filters and balanced lowpass filters for high-data-rate digital communications in planar and integrated RF platforms, and on-chip two-port-absorptive bandstop filters. Furthermore, as key examples of reflectionless RF active devices, millimeter-wave input-absorptive RF amplifiers for beyond-5G wireless scenarios are presented. Cutting-edge applications in antennas, electromagnetic compatibility (EMC), and quantum engineering are also discussed, highlighting the versatility of the reflectionless design philosophy.

A harmonic cancellation technique based on a phase manipulation technique is presented for Ku-band voltage-controlled oscillators (VCO), achieving significant phase noise reduction, especially at the$1/f^{3}$region. The proposed VCO incorporates an auxiliary PMOS transistor with dynamically controlled biasing to generate additional high-order components to compensate for the intrinsic phase difference between the high-order harmonic components of the main PMOS and NMOS cross-coupled transistors, establishing the required$180^{o}$phase difference ($\Delta \theta $) between them. The alignment, facilitated by the proposed technique, significantly suppresses the undesired high-order harmonic components entering the tank’s capacitive path and disturbing its natural frequency. The proposed VCO is fabricated in 65nm CMOS technology, achieving a phase noise of −33.78 dBc/Hz at 1 kHz and -112 dBc/Hz at 1 MHz. The phase noise improvement reaches 5.56 dB at the$1/f^{3}$region compared to a conventional complementary VCO. With a low power consumption of 4.5 mW, the proposed VCO achieves an excellent figure-of-merit (FoM) of −188.4 dBc/Hz with a tuning range of 1.1 GHz (8.1%) operating from 13 GHz to 14.1 GHz.

The traditional method for designing branch-line couplers involves a trial-and-error optimization process that requires multiple design iterations through electromagnetic (EM) simulations. Thus, it is extremely time consuming and labor intensive. In this paper, a novel machine-learning-based framework is proposed to tackle this issue. It integrates artificial neural networks with a self-adaptive differential evolution algorithm (ANNs-SaDE). This framework enables the self-adaptive design of various types of microwave branch-line couplers by precisely optimizing essential electrical properties, such as coupling factor, isolation, and phase difference between output ports. The effectiveness of the ANNs-SaDE framework is demonstrated by the designs of folded single-stage branch-line couplers and multi-stage wideband branch-line couplers.

This paper presents a class of on-chip passive-integrated RF bandpass filters (BPFs) in Gallium Arsenide (GaAs) technology. They exhibit two-port-RF-quasi-absorptive behavior and wideband flat-group-delay responses as main operational features, making them suitable for modern high-date-rate digital-communications systems. Firstly, by means of a reflective one-pole BPF and two shunt identical absorptive bandstop filters (BSFs) in a π-shape topology, an RF BPF with symmetrical quasi-reflectionless response and flat group delay beyond its 3-dB bandwidth (BW) is realized. Subsequently, in order to further improve the stopband attenuation levels of the previously-designed low-order BPF circuit, a higher-rejection counterpart is conceived using two modified single-pole reflective BPF units and three shunt identical absorptive BSF branches. The theoretical responses of both BPFs are obtained from their associated lumped-element-based equivalent circuits. For experimental-demonstration purposes, two GaAs-based proof-of-concept RF BPF prototypes are designed, manufactured, and tested. The two measured absorptive BPFs have 11.58-GHz center frequencies, quasi-reflectionless ranges from DC to 46.02 GHz and from DC to 46.66 GHz, 3-dB-BW ranges from 7.527 to 15.94 GHz and from 8.312 to 15.18 GHz, and maximum group-delay variation of ±0.0068 ns from 5.92 to 16.94 GHz and from 6.316 to 17.58 GHz, respectively.

This paper reports a novel class of RF dual-band bandpass filters (BPFs) with quasi-flat group delay and multiple stopband transmission zeros (TZs). These filters mainly exploit microstrip-to-microstrip (MS-to-MS) vertical transitions on stepped-impedance slotlines. A two-layer dual-band BPF with quasi-flat group-delay response and seven stopband TZs is firstly conceived by properly determining the electrical-length and line-impedance parameters of the constituent slotline sections of its devised stepped-impedance slotline resonator. In order to increase the abruptness of the filter cut-off slopes and the stopband power-rejection levels, a sharper-rejection dual-band BPF composed of several cascaded units is also realized. It includes a stepped-impedance-slotline-based vertical transition, two matching circuits, and two half-wavelength-slotline-based vertical transitions. The RF operational principles of these dual-band BPFs are illustrated through their transmission-line-based equivalent circuit models. Moreover, for validation purposes, a proof-of-concept circuit of the first dual-band BPF is designed and simulated at the electromagnetic (EM) level. The EM-simulated lower and upper passbands are centered at 5.935 and 10.025 GHz with 3-dB fractional bandwidths (FBWs) of 13.65% and 6.98% and maximum group-delay variations of ±0.05 ns from 5.152 to 6.556 GHz and 9.325 to 10.752 GHz, respectively.

The proliferation of Internet of Things (IoT) devices in the era of sixth-generation (6G) wireless communication demands ultra-low power and high-frequency circuit solutions to support sustainable, near-zero energy operation. As IoT devices become more ubiquitous in applications such as smart environments, industrial automation, and wearable electronics, there is a growing need for compact and energy-efficient frequency generators capable of operating in the millimeter-wave spectrum. This study presents the design and analysis of a Digitally Controlled Oscillator (DCO) operating at 45 GHz, conforming to the IEEE 802.11aj standard, and implemented using GlobalFoundries 22-nm fully depleted Silicon-On-Insulator (FD-SOI) technology. The oscillator core adopts a complementary Colpitts topology, chosen for its efficiency and suitability at high frequencies. Frequency tuning is achieved through a digitally controlled switched capacitor array, implemented with lowleakage transmission gates. Operating at a low supply voltage of 0.8 V, the proposed DCO achieves a power consumption of only 5.959 mW and demonstrates excellent spectral purity, with a phase noise of −99.03 dBc/Hz at 1 MHz offset, making it ideal for ultra-low-power mmWave receivers in dense IoT networks.

This paper presents the design and performance evaluation of a low-power, high-frequency Digitally Controlled Oscillator (DCO) incorporating an active inductor, implemented using 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology. Tailored for energy-constrained Internet of Things (IoT) devices-particularly those relying on RF energy harvesting-the proposed DCO achieves a frequency tuning range from 44.78 GHz to 45.35 GHz, while maintaining a total power consumption of less than 12 mW. The integration of an active inductor replaces conventional bulky passive inductors, enabling significant area reduction and improved compatibility with standard CMOS processes. This makes the design highly suitable for compact and scalable on-chip RF systems. Although the design exhibits a moderate phase noise of$-78.96 \text{dBc} / \text{Hz}$at 1 MHz offset, it offers a well-balanced trade-off between power efficiency, frequency performance, and spectral purity. Overall, the proposed DCO architecture demonstrates a viable solution for next-generation, low-power mmWave transceivers in dense IoT networks and other wireless sensor applications.

This paper presents a current-reused coupled oscillator with improved noise circulating technique for phase noise improvement. The proposed current-reused coupled oscillator with order of 2, where the noise circulation oscillator is stacked on top of PMOS cross-coupled oscillator solves the strict trade-off between power consumption and phase noise. The degeneration transistors for noise circulating operations are biased in triode-region instead of in saturation to provide an optimum delay in loop gain, such that the positive and negative phase change in the normalized impulse sensitivity function (ISF) become more symmetric. Thus, the 1/f3phase noise is significantly improved. The voltage-controlled oscillator (VCO) was implemented using CMOS 65nm technology, and the measurement results demonstrated its operation within a frequency range of 15.4–17 GHz (9.8% tuning range). Despite its low power dissipation of 6.3 mW, the VCO design exhibits excellent performance, offering a phase noise of -111.2 dBc/Hz at 1 MHz offset frequency. Furthermore, the proposed VCO attains a figure of merit (FoM) of -187.4 dBc/Hz.

A family of on-chip passive-integrated absorptive flat-group-delay RF bandpass filters (BPFs) in gallium arsenide (GaAs) technology is presented. These wideband BPFs feature broadband quasi-reflectionless behavior along with quasi-constant group-delay responses beyond their associated 3-dB-bandwidth (BW) ranges. Firstly. by means of a$\pi $-shape network composed of a reflective first-order BPF and two shunt identical lossy bandstop filters (BSFs), a two-port-absorptive RF BPF is engineered. To further increase the stopband attenuation levels, the extension of this filter concept to higher-rejection BPFs usingncascaded reflective single-pole BPF units and (${n} +1$) replicas of a shunt lossy BSF is then approached. Subsequently, in order to equip such BPFs with higher-selectivity filtering responses, the development of input- and two-port-reflectionless BPFs with multiple transmission zeros (TZs) is addressed. Moreover, a multi-TZ flat-group-delay BPF with input-absorptive behavior is devised. It exploits a reflective BPF channel, which is shaped by a high-selectivity BPF unit with two close-to-passband TZs and a shunt series-LCresonator that produces an additional TZ, along with a shunt absorptive BSF in a complementary-diplexer-based topology. Finally, by cascading two duplicated high-selectivity BPFs and the associated absorptive BSFs with a modified shunt series-LCresonator in a back-to-back connection, a type of two-port-reflectionless BPF with multiple TZs is further engineered. Following this approach, a modified shunt lossy BSF instead of the previous shunt series-LCresonator is employed in the overall reflectionless BPF to obtain a sharper-rejection passband and flatter group delay versus the corresponding beyond-3-dB BW. The RF operational foundations of these absorptive BPFs are detailed with analyses of their relevant lumped-element-based equivalent circuits. Furthermore, proof-of-concept prototypes for the five suggested RF BPFs are simulated, built, and measured to experimentally validate their design concepts for application in power-efficient high-data-rate digital-communication systems.

This paper proposes an isolated gate driver that incorporates an enhanced common-mode transient immunity (CMTI) technique to effectively suppress common-mode transient (CMT) noise. Additionally, the approach leverages the CMT noise to enable on-the-fly deadtime (DT) control at the transmitter. Experimental results demonstrate the DT jitter compensation circuit reduces high-frequency carrier (500 MHz) jitter by 10.6%, the efficiency is improved by 11.5%, and the CMTI is improved from 184 kV/μs to 208 kV/μs.

An input-reflectionless RF amplifier operated at millimeter-wave (mm-wave) frequencies is reported in this paper. Its design methodology allowing it to attain a broadband RF-input-power-absorption behavior is detailed through the circuit analysis of the designed amplifier. For practical-demonstration purposes, a single-stage cascode input-reflectionless amplifier chip is fabricated and tested using 45-nm silicon-on-insulator (SOI) CMOS technology. Under a 1.2-V power supply, the DC-power consumption of the designed amplifier is 5.3 mW. It has a peak gain of 5.3 dB at 31 GHz. Moreover, the measured input 1-dB compression point (P1dB) is around -2.6 dBm. The measured input-power-matching levels of the designed amplifier are higher than 10 dB from DC to 60 GHz. In addition, a two-stage amplifier is also designed in simulation by cascading a conventional cascode amplifier with the proposed single-stage reflectionless amplifier. Simulation results show that a good improvement in terms of signal-to-interference ratio is achievable. The core size of the designed input-reflectionless amplifier is only 0.25 × 0.7 mm2.

This paper presents a high-order multilayer RF filter with wideband quasi-flat group-delay response and sharp multi-transmission-zero (TZ) stopbands. It is composed of three in-series-cascaded stages of low-order/single-unit input-absorptive wideband bandpass filters (BPFs). Its constituent BPF unit, which is based on a modified two-layer microstrip-to-microstrip vertical transition and a shunt resistivelyterminated microstrip line and exhibits quasi-flat group-delay response and broadband input-absorptive capabilities, is firstly discussed. Due to the employed short-circuit-ended two-section microstrip stub in the modified vertical transition, two close-to-passband TZs are realized to obtain a sharper-rejection BPF response. To achieve highly-attenuated multi-TZ stopbands, a high-order wideband quasi-flat-group-delay BPF with three in-series-cascaded single-unit BPFs using different impedanceparameter values for the short-circuit-ended microstrip stubs is then studied. For experimental-validation purposes, a 2-GHz proof-of-concept microstrip prototype in a two-layer substrate is simulated, built, and tested. The measured input-absorptive BPF is centered at 1.956 GHz with 3-dB absolute bandwidth of 0.828 GHz and maximum group-delay variation of ± 0.05 ns from 1.387 to 2.618 GHz (i.e., 1.231-GHz absolute bandwidth).

An inductorless differential Low Noise Amplifier (LNA) with high linearity, designed for geofencing applications, is presented. The LNA incorporates gm-boosting, linearity optimization, and noise-cancelling stages. A complementary derivative superposition technique is used for gm-boosting, while a common-source noise-cancelling path is employed to implement the linearity enhancement stage. The design uses a differential structure for linearity optimization, addressing inherent stability issues associated with the technique. Implemented in 65nm technology, the LNA occupies a chip area of 0.037 mm2and achieves a noise figure (NF) of 3.03 dB, a peak gain of 16.78 dB, and an IIP3 linearity of 9.94 dBm, with a power consumption of 28 mW. The LNA demonstrates good stability and process variation tolerance.

A class of reflectionless RF bandpass filters (BPFs) with wideband quasi-constant in-band group-delay response in transmission for high-data-rate digital-communication systems is presented. These BPFs are developed by exploiting multilayer wideband microstrip-to-microstrip vertical transitions and lossy multi-section microstrip lines in complementary-diplexer-based architectures. A two-port-reflectionless wideband BPF with low-in-band-variation equi-ripple-type group-delay characteristics is firstly realized by using two resistively-terminated one-section microstrip lines. To further flatten its passband group delay, its counterpart based on lossy two-section microstrip lines is then conceived to attain extremely-flat wideband group-delay pattern. Subsequently, by means of a modified wideband microstrip transition with a short-circuit-ended two-section microstrip line and a resistively-terminated two-section microstrip line, an input-reflectionless BPF with two close-to-passband transmission zeros (TZs) and wideband in-band flat group-delay profile is reported. In order to obtain a higher-order flat-group-delay wideband BPF response with more TZs, its structure shaped by two in-series-cascaded units of the previous input-absorptive BPF section with two TZs is engineered, in which different impedance values for their constituent short-circuit-ended microstrip lines are utilized. The operational foundations of all the proposed wideband flat-group-delay RF BPFs are described in detail. Furthermore, for practical-validation purposes, three 2-GHz microstrip prototypes of these reflectionless wideband RF BPFs with quasi-constant group-delay responses beyond their 3-dB absolute bandwidths (BWs) are designed, simulated, manufactured, and characterized.

In this work, a ten-way power-combined power amplifier is designed using a load modulated balanced amplifier (LMBA)-based architecture. To provide the required magnitude and phase controls between the main and control-signal paths of the LMBA, an unequal power splitter and a phase compensation network are proposed. As proof of concept, the designed power amplifier is implemented in a 45-nm SOI CMOS process. At 40 GHz, it delivers a 25.1 dBm$\text{P}_{\text {sat}}$with a peak power-added efficiency (PAE) of 27.9%. At 6-dB power back-off level, it achieves 1.39 times drain efficiency enhancement over an ideal Class-B power amplifier. Using a 200-MHz single-carrier 64-QAM signal, the designed amplifier delivers an average output power of 16.5 dBm with a PAE of 13.1% at an EVMrmsof −23.9 dB and ACPR of −25.3 dBc. The die size, including all testing pads, is only 1.92 mm2. To the best of the authors’ knowledge, compared with the other recently published silicon-based LMBAs, this design achieves the highest$\text{P}_{\text {sat}}$.

In this work, a wideband millimeter-wave (mm-wave) power amplifier (PA) is reported. To provide excellent input/output impedance matching across broadband, sufficient output power and high power-added efficiency (PAE), a balanced amplifier (BA)-based architecture is used in designing this PA. In particular, an edge-coupled quadrature coupler is designed as its RF-power-division/combination block, and its performance in terms of magnitude/phase balance error is minimized throughout a relatively wide bandwidth. A PA prototype is fabricated in 0.13-$\mu \text{m}$SiGe HBT technology and tested. Under a 1.6-V power supply, the variation of small-signal gain is less than 3 dB within 20-40 GHz, which is equivalent to more than 66% fractional 3-dB bandwidth. Within this frequency range, at least 15.8 dBm saturated output power could be delivered with the peak PAE higher than 16.8%. The designed PA supports a single-carrier 200-MHz 64-quadrature amplitude modulation (QAM) with higher than 12.8-dBm average output power, while still maintaining an error vector magnitude (EVM) below −25 dB at 30 GHz. The size of the designed compact-size PA, including all pads, is only 0.7 mm$\times1.3$mm.

The millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm2.

A design methodology using quasi-lumped elements for compact millimeter-wave on-chip bandpass filter (BPF) is presented in this work. To implement BPF using this approach, a novel inductor cell is presented first and then using this cell along with metal-insulator-metal (MIM) capacitors, two BPFs are designed. For the purpose of proof-of-concept, all three designs are implemented and fabricated in a standard 0.13-μm (Bi)-CMOS technology. The measurements show that the inductor cell generates a notch at 47 GHz with a chip size of 0.096 × 0.294 mm2without pads. Moreover, the 1st BPF has the center frequency at 27 GHz with an insertion loss of 2.5 dB and it has one transmission zero at 58 GHz with a peak attenuation of 23 dB. Unlike the 1st design, the 2nd design has two transmission zeros. The center frequency of this BPF is located at 29 GHz with a minimum insertion loss of 3.5 dB. Without the measurement pads, the chip sizes of the two BPFs are 0.076 × 0.296 mm2and 0.096 × 0.296 mm2, respectively.

In this work, an on-chip bandpass filter (BPF) with ultra-wideband, low insertion loss, sharp selectivity and excellent in-band flatness is achieved using a novel design approach based on a quasi-lumped-element method. This approach simply utilizes folded metal strip lines with metal-insulator-metal (MIM) capacitors. To understand the principle of the presented design approach, theoretical analysis is given by means of a simplified equivalent LC-circuit model. Using the analyzed results with a full-wave electromagnetic (EM) simulator to guide the design, a BPF is implemented and fabricated in a standard 0.13-μm (Bi)-CMOS technology. The measurements show that a return loss of better than 10 dB is obtained from 13.5 to 32 GHz. Furthermore, the insertion loss of less than 2.3 dB is achieved with less than 0.1 dB in-band magnitude ripple. The BPF size without measurement pads is only 0.148 mm2(0.37 × 0.4 mm2).

In this work, a new type of miniaturized on-chip resonator using an inductively-coupled structure is presented. The resonator is constructed by two spiral conductors that are implemented using two different metal layers. Since the two conductors are identical but placed in different rotating pattern, a kind of inductive coupling called inverting coupling will be introduced in addition to the broadside capacitive coupling. To fully understand the working mechanism of the resonator, simplified LC equivalent-circuit models and thorough analysis are provided. To further demonstrate the feasibility of the proposed miniaturized resonator in practice, two bandpass filters, namely a 1st-order and 2nd-order, are designed and fabricated in a standard 0.13-μm (Bi)-CMOS technology. Good agreements between simulation and measurement have obtained, which verify that the presented design approach is suitable for miniaturized on-chip passive design.

The well-known Internet of Things (IoT) is recently being considered for critical missions, such as search and rescue, surveillance, and border patrol. One of the most critical issues that these applications are currently facing is how to correctly distinguish between human and animal targets in a cost-effective way. In this paper, we present a relatively low-cost, but robust approach that uses a combination of device-free sensing (DFS) and machine-learning technologies to tackle this issue. In order to validate the feasibility of the presented approach, a variety of data is collected in a cornfield using impulse-radio ultra-wideband (IR-UWB) transceivers. These data are then used to investigate the influence of different statistical properties of the radio-frequency (RF) signal on the accuracy of human/animal target classification. Based on the probability density function of different statistical properties, two distinguishing features for target classification are found, namely, standard deviation and root mean spread delay spread. Using them, the impact on the classification accuracy due to different classifiers, number of training samples, and different values of signal-to-noise ratio is extensively verified. Even with the worst case, the classification accuracy of the system is still better than 91% in terms of distinguishing between human and animal targets (including goats and dogs), which indicates that the presented approach has a great potential to be deployed in the near future.

Foliage penetration (FOPEN) has been found to be a critical mission for a variety of applications, ranging from surveillance to military. Recently, an emerging technology, namely wireless sensor network (WSN)-based device-free sensing (DFS), has been introduced to the domain of FOPEN. This technology only utilizes radio-frequency signals for target detection and classification; thus, no additional hardware is required, just a wireless transceiver. Although the feasibility of using this technology for human detection indoors has been explored to some extent, it is questionable if the same technology can be transferred to outdoors. As far as FOPEN is concerned, the impact of seasonal variations on detection accuracy can be severe. To address this concern, in this paper, an experiment is conducted in four seasons, and how to ensure reasonable detection accuracy with seasonal variations is intensively investigated. To fully evaluate the potential of using the WSN-based DFS for FOPEN, an impulse-radio ultrawideband technology-based prototype is used to collect data samples in different seasons. Unlike the conventional approach based on a combination of statistical properties of received-signal strength and a support vector machine, this approach adopts two special measures for performance enhancement. One measure is to use a higher order cumulant (HOC) algorithm for feature extraction, so that the impact on detection accuracy due to unwanted clutters can be minimized. The other one is to determine the optimal parameters of the classifier by means of a flower pollination algorithm. Consequently, the adverse effects on detection accuracy due to variations of weather conditions in four seasons can be accommodated. According to the experimental result, it is shown that the average classification accuracy of the presented approach can be improved by at least 20% under all seasons with an ensured robustness.

In this letter, the possibility of using device-free sensing (DFS) technology for personnel detection in a foliage environment is investigated. Although the conventional algorithm that based on statistical properties of the received-signal strength (RSS) for target detection at indoor or open-field environment has come a long way in recent years, it is still questionable if this algorithm is fully functional at outdoor with the changing atmosphere and ground conditions, such as a foliage environment. To answer this question, a variety of the measured data have been taken using different targets in a foliage environment. Applying these data along with support vector machine, the impact on detection accuracy due to different classification algorithms is studied. An algorithm that based on the extraction of the high-order cumulant (HOC) of the signals is presented, while the conventional RSS-based one is used as a benchmark. The measurement results show that the classification accuracy of the HOC-based algorithm is better than the RSS-based one by at least 17%. Moreover, to ensure the reliability of the HOC-based approach, the impact on classification accuracy due to different numbers of training samples and different values of signal-to-noise ratio is extensively verified using experimentally recorded samples. To the best of our knowledge, this is the first time that a DFS-based sensing approach is demonstrated to have a potential to distinguish between human and small-animal targets in a foliage environment.

A transformer-coupled frequency quadrupler with 50% bandwidth is designed in a 0.25μm SiGe process. The quadrupler covers an output frequency range from 36GHz to 60 GHz with a total power consumption of 38.5mW for a supply voltage of 2.5V. To fulfil the requirement of harmonic suppression, a novel on-chip asymmetrical Marchand balun structure is adopted to compensate the phase and amplitude errors across a wide bandwidth, so that the 3rd- and 5thharmonic suppressions of more than 30-dB can be achieved. The transformer-coupled approach along with a common-base configuration is adopted to enlarge the bandwidth of the multiplier.

This paper outlines the popular circuit tuning strategies reported for the implementation of reconfigurable low-noise amplifiers (LNAs). It presents a continuously-tuned LNA intended for multi-standard applications as well as enhancing the yield of conventional narrowband LNAs. The presented LNA is designed and implemented in a 0.25μm silicon-on-sapphire (SOS) CMOS process. It uses MOS-varactors at the output to continuously tune its load resonance frequency and input matching frequency without the need of a tunable input network, achieving optimized power consumption and noise figure (NF). The post-layout simulations show that the designed LNA can be continuously tuned from 2.6 GHz to 3.5 GHz. Over this frequency range, an input IP3 of of -12 dB, gain of 17 dB and a NF of less than 2 dB have been achieved with 3.4 mW of power consumption at 1.8V.

The design and implementation of a CMOS continuous-time multiple loop feedback (MLF) leap frog (LF) filter is described. The filter is implemented using a fully.differential linear, low voltage operational transconductance amplifier (OTA). PSpice simulations using a standard TSMC 0.18μm CMOS process with 1.8V power supply have shown that the cut-off frequency of the filter ranges from 455MHz to 780MHz and dynamic range is about 58dB. The group delay is less than 5% over the whole tuning range; the maximum power consumption of the filter with gain boost is only 240mW.

We propose an easily implemented and low-cost design-for-testability scheme for OTA-C filters based on an oscillation-based test (OBT) methodology. The OBT method is a vectorless output test strategy easily applicable to built-in self-test. During test mode, the filter under test is converted into an oscillator by establishing the oscillation condition in its transfer function. The oscillator frequency can be measured using digital circuitry and deviations from the cut-off frequency indicate faulty behaviour of the filter. The proposed method is suitable for both catastrophic and parametric fault diagnosis and is effective in detecting single and multiple faults. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of two-integrator loop, Tow-Thomas and KHN OTA-C filters. Simulation results for 2ndorder filters using a 0.25μm CMOS technology show that the proposed oscillation-based test strategy has more than 96% fault coverage and, with a minimum number of extra components, requires a negligible area overhead.

A 300MHz CMOS seventh-order linear phase gm-C filter based on a current-mode multiple loop feedback (MLF) leap-frog (LF) structure is realized. The filter is implemented using a fully-differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. PSpice simulations using a standard TSMC 0.18μm CMOS process with 2.5V power supply have shown that the cut-off frequency of the filter can be tuned from 260MHz to 320MHz and dynamic range is about 66dB. Group delay ripple is approximately 4.5% over the whole tuning range and maximum power consumption is 210mW.