This paper proposes a quad-core, quad-mode millimeter-wave (mmWave) voltage-controlled oscillator (VCO) utilizing electromagnetic hybrid coupling. This design achieves a wide frequency tuning range and low phase noise, fulfilling the needs of integrated sensing and communication (ISAC) systems. The oscillator addresses the challenge of concurrent oscillations in multi-mode switching oscillators by implementing a switched transconductance network. The VCO also employs a controllable tail transistor array to suppress flicker noise up-conversion across a wide bandwidth, effectively reducing the 1/f3corner frequency and enhancing the phase noise performance. The VCO is fabricated in a 55-nm CMOS process occupying a core area of 0.08 mm2. Measurement results show that the VCO achieves a tuning range of 51.9% spanning from 18.7 to 31.8 GHz, and a phase noise of -110.0 dBc/Hz at 1 MHz offset while consuming 8.4 mW of power, leading to a figure of merit (FoM) of 186.2 dBc/Hz and FoMTof 200.5 dBc/Hz at 1 MHz offset.

A 32 fs RMS jitter oversampling phase-locked loop (OSPLL) exploiting a high-gain cross-switching phase detector (CSPD) is proposed. The over-sampling PLL increases sam-pling frequency by 4x, reducing the in-band phase noise and overcoming the loop bandwidth limitation due to the reference frequency. Leveraging the increased loop bandwidth, the noise contribution of the voltage-controlled oscillator (VCO) is sig-nificantly suppressed. The high-gain CSPD adopts a common-mode sampling technique with time interleaving switches to ensure that the reference clock is sampled only at the maximum slew rate. The CSPD with a higher gain facilitates reducing the noise contribution from the phase detector (PD) and the transconductance cell. Additionally, an RC poly-phase filter (PPF) is employed to generate quadrature clocks, avoiding the deterioration of the PLL's low offset frequency phase noise. The PLL is implemented in a 40-nm CMOS process. Simulation results show that the PLL achieves a 32 fs RMS jitter integrated from 10 kHz to 100 MHz and a power consumption of 6.5 mW, resulting in an$FoM_{jitter}$of -261 dB. At 3.84 GHz frequency, the in-band phase noise is -136.8 dBc/Hz at 100 kHz offset.

This paper proposed a cascaded harmonic enhanced injection-locked frequency tripler fabricated in a 40-nm CMOS process. In order to suppress the fundamental signal and the second harmonic signal, an injection-locked doubler is explored, and then the obtained ×2 frequency signal is mixed with the fundamental signal to realize the third harmonic signal and then the third harmonic signal is injected into the tank of the injection-locked frequency selection network to improve the output power. The tripler achieves a fundamental suppression over -69 dBc and a second harmonic suppression over -66 dBc. The output power over the entire locking range from 71.5 to 86.7 GHz is larger than 5.5 dBm. The chip occupies a die area of 0.25 × 0.35mm2and dissipates 20 mW of power.

This paper presents a continuous frequency switching zig-zag voltage-controlled oscillator (VCO) to overcome the frequency discontinuity problem during the band switching process in multi-band wideband VCOs. Complementary PMOS and NMOS varactors are explored to realize opposite VCO tuning gains with high linearity. The VCO reduces the nonlinearity of the transmitted chirp in frequency-modulated continuous-wave (FMCW) radars, improving the range resolution. Implemented in a 40-nm CMOS technology, the proposed zig-zag multi-band VCO shows a simulated maximum peak frequency error of 10 MHz over 23.4-27.6 GHz frequency range, a −106.6 dBc/Hz phase noise at 1 MHz offset, and a −183.1 dBc/Hz FoM while consuming 12.69 mW power.

This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially active second-stage comparison and$2\times $time-domain latch interpolation (TDI) to reduce power consumption and avoid extensive calibrations. To enhance the conversion speed of the second-stage structure, the stringent timing constraint is resolved by a 25%–75% duty-cycle clock scheme, a 0.5-bit redundancy in the first comparison stage, and an embedded second-stage slice selection logic. The bandwidth requirements of the track-and-hold (T/H) and T/H buffer under the 25%–75% duty-cycle clock are analyzed. An on-chip successive-approximation (SA)-based comparator offset calibration scheme utilizing FDSOI back-gate bias is also developed, providing sufficient calibration range without impairing comparator speed. The measured prototype achieves a signal-to-noise and distortion ratio (SNDR) of 32.8 dB and a spurious-free dynamic range (SFDR) of 41.82 dB at Nyquist frequency while consuming 15.07 mW power, translating into a Walden figure-of-merit (FOM) of 84.5 fJ/conversion-step.

This paper presents a wideband millimeter wave (mmW) LNA fabricated in a 55-nm CMOS process. Inter-stage transformer peak splitting and gain equalization techniques are proposed to improve bandwidth and gain flatness. A transformer- based anti-phase coupling (TBAC) method is developed to enhance effective transconductance boosting, while optimizing noise figure (NF). The LNA achieves a peak gain of 11.8 dB with a gain variation of less than ±0.8 dB, a flat gain bandwidth (FGBW) of 15 GHz (66-81 GHz) and a BW-3dB of 20 GHz (64-84 GHz). The measured NFmin is 5.09 dB at 75 GHz and the input-referred 1dB compression point (IPidB) is -5.8 dBm at 78 GHz. The LNA consumes 40 mA from 1 V power supply.

This paper presents a 6-bit 20 GS/s 2-way time-interleaved (TI) flash analog-to-digital converter (ADC) in a 28-nm FDSOI CMOS technology. Leveraging threshold voltage control via back-gate bias in FDSOI, an automatic comparator offset calibration scheme is developed, which does not require extra transistor pairs or capacitive loads in signal path, thus avoiding comparator speed degradation. To alleviate channel mismatch-induced errors in highly interleaved structure while maintaining a reasonable power efficiency, the ADC adopts a two-way TI structure with the subADC working at 10 GS/s. To further improve the ADC power efficiency, a 1-bit voltage-domain interpolation is utilized. The proposed flash ADC achieves a SNDR of 31.2 dB at Nyquist frequency with a power consumption of 204 mW, translating into a figure-of-merit (FOM) of 344 fJ/conv.-step.

This paper presents a low-power silicon photomultiplier (SiPM) readout front-end with on-chip fast pulse generation and successive-approximation-register (SAR) ADC. The front-end mainly consists of a current buffer with an on-chip C-R high pass filter (HPF), a charge integrator, a current discriminator, and a 10-bit low-power SAR ADC. The current-mode buffer offers a low input impedance thus achieving a high input bandwidth. The on-chip HPF shortens the width of the SiPM's long-tailed single photo-electron (SPE) response to generate the fast pulse signal, which allows the current discriminator to suppress the uncertainty of timing measurement and helps to achieve a better coincidence resolving time (CRT). Compared with off-chip fast pulse generators, no additional I/O pin is required facilitating compact multi-channel SiPM readouts. By reusing the charge integration capacitor as the sampling capacitor of the SAR ADC, the power-hungry charge sensitive amplifier (CSA) is eliminated. The front-end is designed in a 0.18 μm 1P6M standard CMOS technology, and has a low power consumption of 4 mW. The on-chip HPF reshapes the long-tailed SPE pulse width from 50 ns to 3 ns. At 1 MS/s, the SAR ADC consumes 132 μW from a 1.8 V supply, and achieves a SNDR of 58.11 dB and a SFDR of 72.47 dB, respectively.