In this paper we consider using memristors for high-dimensional computing that requires very large associative memories, but generally has good tolerance to nonidealities in the implementation medium. To consider such computing with existing devices, we present measurements of a tantalum oxide memristor that can be programmed to resistance values between high resistance state and low resistance state. Based on the measurements, we estimate the variation in the resistance states, and describe how a pseudo-analog programming operation can be used for trimming ON-resistance values. Finally, we discuss how different memory initialization and programming approaches affect the reliability of an associative search.

We recently mapped an algorithm for online learning of linear subspaces using local learning rules to an analog array computing framework. In this work we consider a simplified version of this algorithm which can be realized as a mixed-mode computing array. This allows similar learning results as the unmodified algorithm and is designed to allow large-scale test circuit fabrication with commercially available technologies. We demonstrate by numerical simulations of the mixed mode learning system that less than ten-bit resolution in the considered digital circuitry is sufficient for useful learning; such resolution allows efficient implementation of the related analog computations. The presented circuit has practical applications e.g. in signal classification, adaptive compression, and compressive sensing in low-power devices.

This article provides a survey and a general methodology for coexistence studies between digital terrestrial television (DTT) and mobile broadband (MBB) systems in the ultra high frequency (UHF) broadcasting band. The methodology includes characterization of relevant field measurement scenarios and gives a step-by-step guideline on how to obtain reliable field measurement results to be used in conjunction with link budget analyses, laboratory measurements, and simulations. A survey of potential European coexistence scenarios and regulatory status is given to determine feasible future use scenarios for the UHF television (TV) broadcasting band. The DTT reception system behavior and performance are also described as they greatly affect the amount of spectrum potentially available for MBB use and determine the relevant coexistence field measurement scenarios. Simulation methods used in determining broadcast protection criteria and in coexistence studies are briefly described to demonstrate how the information obtained from field measurements can be used to improve their accuracy. The presented field measurement guidelines can be applied to any DTT-MBB coexistence scenarios and to a wide range of spectrum sharing and cognitive radio system coexistence measurements.

Summary form only given. The Von Neumann bottleneck originates from the low bandwidth between processing and memory. One paradigm that could ease the bottleneck is Computing-in-Memory (CiM), where the same elements store logic values and perform logical operations on them in the same physical location. Here, presented are implementations of the K-means clustering algorithm on a Memristive Logic Array-based CiM implementation and a Machine Learning specific Transport-Triggered Architecture (TTA) processor implemented on 28nm FDSOI technology and operating at 0.35V. While running K-means, the Memristive CiM is 5,7 times faster and uses 2,3 times less energy than the TTA processor. However, the average power consumption of the MLA is 2,5 times the power of the TTA.

The primary aim of this work is to provide new tools for machine learning and reasoning within a framework of computing with holistic data representations. Specifically, we demonstrate recursive construction of mappings and functions in high-dimensional computing with random vectors - a connectionist computing model which provides benefits similar to neural networks, but allows compositional learning. The computational operations considered in this work are applicable in learning by generalizing from small sets of example data. We demonstrate their use by constructing a simple reasoning model which learns modulo 10 addition and subtraction from a minimal set of examples. Finally, we give examples on how the presented computational operations can be used to compose and manipulate more complex structures in computing with high-dimensional random vectors.

We describe how an analog associative memory architecture can be used to infer time-variant states of a hidden Markov model (HMM), demonstrating computation of forward probabilities, backward probabilities, smoothing, and the Viterbi algorithm. This type of computing is well suited for implementation in array computing architectures, and the necessary elementary computations have been demonstrated in previous work. We consider the effect of limited accuracy in storage and computing elements on the inference reliability, and demonstrate that although the computation is iterative, reliable operation is not significantly affected by error accumulation.

Distributed associative memory architectures store data in multiple locations redundantly, and are thus robust to circuit irregularities and noise. In this paper we explain ways to store the occurrence statistics of vectors in a distributed memory. Sparse data vectors are used to maximize vector capacity, and binding of sparse vectors is used to combine elementary symbols into symbols that represent larger entities. The use of such statistics is demonstrated with an on-line learning example that uses redundancy reduction. We show that occurrence statistics can be represented with distributed Willshaw-type associative memories sing hardware counters, as well as symbolically using two-bit memory cells.

In this paper we present a CMOS implementation of a 512×512-cell Associative Content Addressable Memory (ACAM) in 180 nm CMOS. The memory can be operated either as an associative CAM or it can be configured into a Willshaw memory for operating with sparse data. The vector matching operation can use a tunable hit threshold or the strongest hit can be selected with a winner-take-all (WTA) network. Built-in row and column circuitry can perform logic operations on the contents of the row and column memories. The operation of the circuit is verified experimentally with an example on computing with random vectors.

In this work we consider the implementation of nondeterministic finite automata in autoassociative memory, and demonstrate mapping and operating such automata in an associative content-addressable/Willshaw-type memory circuit presented in a companion paper. This topic is relevant in the broader scope of in-memory computing, and offers a simple, flexible, and computationally efficient way of implementing nondeterministic finite automata using existing general-purpose associative memory hardware.

We show a Field-Programmable Analog Array complemented with post-processed memristors (FPAA/memristor hybrid circuit), and present it as a platform for analog signal processing. The FPAA is fabricated on CMOS and uses floating-gate transistors (FGT) to realize programmable wiring fabrics and analog computing resources. The memristors, post-processed on top of the FPAA, are analog, which means that their conductance can be programmed in a continuous fashion. We highlight the key differences between FGTs and memristors, and discuss how analog signal processing tasks could be divided between them. Experimental results of the FPAA-memristor hybrid circuit are presented.

Associative memories, in contrast to conventional address-based memories, are inherently fault-tolerant and allow retrieval of data based on partial search information. This paper considers the possibility of implementing large-scale associative memories through memristive devices jointly with CMOS circuitry. An advantage of a memristive associative memory is that the memory elements are located physically above the CMOS layer, which yields more die area for the processing elements realized in CMOS. This allows for high-capacity memories even while using an older CMOS technology, as the capacity of the memory depends more on the feature size of the memristive crossbar than on that of the CMOS components. In this paper, we propose the memristive implementations, and present simulations and error analysis of the autoassociative content-addressable memory, the Willshaw memory, and the sparse distributed memory. Furthermore, we present a CMOS cell that can be used to implement the proposed memory architectures.

In a cognitive radio system, awareness of the prevailing radio environment of the primary network, such as digital terrestrial television, is important since it governs the emission limits for the secondary system devices. Field strength estimates of the primary network are typically computed using terrain based radio propagation models, or by using univariate interpolation techniques to approximate the field strength from measurement samples. However, the limited geographical information or small numbers of measurement samples sets a restriction on the accuracy of the field strength estimates. In this paper, we propose a multivariate interpolation method for incorporating field measurements into radio propagation models. The proposed method shows considerable increase in estimation accuracy compared to previously presented methods. The model is verified using field measurement data from an operational digital terrestrial television network.

We propose three new synthesis methods for memristive implication logic and compare these with each other and with a basic method which was originally proposed in [5]. The results show that by using complementary representation of variables and multi-input operation, the lengths of computational sequences required for computing a given Boolean function are significantly reduced; for the three-input parity function this reduction is approximately 85 percent compared to the basic method.

We determine an explicit procedure for representing any Boolean expression in a recursive form which can be realized using memristive devices, and demonstrate how the truth value of any Boolean expression can be determined using no more than two computing memristive devices. We present an algorithm which can be used to significantly reduce the number of implications required for representing a specific Boolean expression, and consider device-specific benefits in terms of reducing the lengths of computational sequences.

We describe a generic exponential model with four parameters for thin-film memristive devices. This model is used to analyze the time dependency of the threshold voltage which defines the transition between non-programming and programming phases of the device. A relationship between timescale of operation and threshold voltage is derived. Furthermore, self-terminating programming is considered using the results of this analysis. Finally, the effect of parameter variations on the threshold voltage is analyzed.

In this paper, a novel approach to computing arbitrary Boolean functions using a binary-state cellular neural/nonlinear/nanoscale network (CNN) architecture with local static memory is presented. We define explicitly how to map a given Boolean function and its input values to the cells of a specific type of binary CNN, and the global rules used to perform parallel calculations. Each of the computation steps can be performed asynchronously. Additionally, the total CNN area is readily split into subsections, each of which perform individual computations of different Boolean functions. The main benefits of our approach are simple implementation of arbitrary Boolean functions, built-in parallelism both in local and global scale of the computation and the possibility for asynchronous operation.

In this paper, we consider aggregated Markov processes, which are a subclass of hidden Markov models. Artificial limitations are set on the state transition probabilities of the models to make them renewal processes; these restrictions are then used to find efficient methods of parameter estimation for realizations of the considered models. We apply these models in simulating the performance of Digital Video Broadcasting - Handheld (DVB -H). The parameters of the packet error models are approximated as functions of the time-variant received signal strength and speed of a mobile vehicular DVB-H receiver, and it is shown that useful results may be achieved with the described packet error models especially in simulating mobile reception in field conditions.

Digital video broadcasting for hand held terminals (DVB-H) is a broadcast system designed for high-speed data transmission in highly dispersive mobile channel conditions. In this paper, methods of reproducing the statistical properties of measured DVB-H packet error traces are presented. Statistical and finite-state modeling approaches are found to be suitable for simulating the error performance of a DVB-H system operating in typical urban channel conditions. Evaluation of these models focuses on the accuracy of the models in replicating the high-order statistical properties of measured DVB-H transport stream error traces. Also, the effect of these error statistics on the DVB-H link layer frame error rate is considered.

This paper describes a class of finite-state packet error models that use mixtures of geometric distributions to approximate the statistics of measured packet error traces. Functional methods of determining the model parameters based on observed error statistics are proposed and implemented. Specific models from this class are constructed as examples and applied in simulating a digital video broadcasting system for handheld terminals (DVB-H). The models are then evaluated based on their statistical accuracy and simulation performance. It is determined that the new model evaluation approach offers improvement over earlier implementations