A ring oscillator based test structure with special power multiplexing to allow accurate active and standby (leakage) power measurements with minimal test chip pin count is presented. This structure is used to validate radiation hardened by design (RHBD) standard cell library gates for TID hardness and delay. Additionally, the performance of standard commercial two-edge gates and their annular counterparts are also compared experimentally. The gate delay and energy per transition is shown to be significantly increased for some RHBD gates over their two-edge counterparts. Large ring oscillator delay variations are also shown, even with all test die from the same wafer.

Measurement and extraction of as fabricated SRAM cell variability is essential to process improvement and robust design. This is challenging in practice, due to the complexity in the test procedure and requisite numerical analysis. This work proposes a new singleended test procedure for SRAM cell write margin measurement. Moreover, an efficient decomposition method is developed to extract transistor threshold voltage (VTH) variations from the measurements, allowing accurate determination of SRAM cell stability. The entire approach is demonstrated in a 90nm test chip with 32K cells. The advantages of the proposed method include: (1) a single-ended SRAM test structure with no disturbance to SRAM operations; (2) a convenient test procedure that only requires quasistatic control of external voltages; and (3) a non-iterative method that extracts the VTH variation of each transistor from eight measurements. The new procedure enables accurate predictions of SRAM performance variability. As validated with 90nm data of write margin and data retention voltage, the prediction error from extracted VTH variations is < 4% at all corners.