In recent years, simulation-based optimization methods for analog integrated circuit design parameters optimization (a.k.a sizing) have attracted extensive research interest. Currently, researchers primarily focus on developing efficient algorithms while paying little attention to decision spaces. This work focuses on the decision space, aiming to improve the efficiency and usability of the parameters optimization task. linear and dynamic circuits. We also handle circuit constraints by directly fine-tuning search bounds. Second, taking the high-fidelity EKV model, we demonstrate the unique characteristics of the electrical design space and prove that a bijective relationship exists between the two decision spaces. Third, we propose a multi-form (MF) optimization framework that simultaneously optimizes the physical design space and electrical design space. This framework avoids the choice of decision space and enhances the algorithm’s optimization efficiency by transferring candidate solutions between two decision spaces. Also, we propose to solve the MF optimization task with Bayesian optimization and population-based algorithms. The proposed sizing framework is verified on three typical analog circuit sizing tasks: single-objective, multi-objective, and yield optimization problems. The result and ablation study show that the proposed framework consistently achieves better results compared to traditional single-space optimization methods, with significantly fewer iterations.

Bayesian optimization (BO) is popular for a analog circuit sizing problem recently. However, BO can only work well in small-scale circuit. Scaling BO to common circuit optimization (typically dimension > 10) is difficult due to the curse of dimensionality. In this article, we proposed a new BO algorithm (cBO), which can scale BO to more larger scale circuit and improve the optimization result. First, according to the fact that a specification of the analog integrated circuit is mainly determined by a few transistors, dropout strategy is adopted in our algorithm. At each iteration, only a subset of selected variables to be optimized. A variables selection strategy based on mutual information analysis and a new fill-in strategy are proposed. Second, the$g_{m}/I_{D}$methodology-based optimization strategy is proposed. Optimization variables are not width and the length of transistors, but$g_{m}/I_{D}$,$I_{D}$and length.$g_{m}$,$I_{D}$and$g_{m}/I_{D}$have a direct relationship to circuit performance. This is equivalent to search in circuit feature space, which could achieve better performance and handle constraints more easily. Four commonly used circuits, including low dropout regulator, two stage amplifiers, Bandgap voltage reference (VR), and VR are used for validation. Compared with other high-dimensional BO, common BO, and commercial tools (Cadence ADE_GXL), the proposed algorithm is found to produce the best optimization result and best stability. And, the ablation study shows the effectiveness and efficiency of two ingredients of the proposed algorithm.

This paper proposes a soft-start method with the features of a small on-chip capacitor and start stability for dc–dc converters. During the soft-start process, a slowly and linearly ramped-up voltage reference is generated based on the principle of the small on-chip capacitor charged by an oscillator-controlled pulse current to replace the normal reference. Meanwhile, the switching frequency is also reduced so that the inductor current has more time to decay and massive inrush current can be avoided. However, in this way, the system may be unstable in that the bandwidth could not keep less than 1/7 of the reduced switching frequency. In this paper, an error amplifier (EA) with gain-degeneration is proposed to solve this problem. When the switching frequency is reduced, the gain of the EA is also reduced and the bandwidth becomes narrower accordingly. A dc–dc converter using the proposed soft-start method has been implemented with a 0.5-$\mu{\rm m}$CMOS process. Experimental results show that a soft-start period of 600$\mu{\rm s}$is achieved with an on-chip capacitor of 15 pF. Furthermore, both the output voltage and inductor current rise smoothly without oscillation and overshoot during the startup process.