Existing hardware emulators use either FPGA or Boolean processors, which suffer from long compile time and poor debuggability (FPGA-based), or low emulation performance (Boolean processor-based). This work presents Sphinx, a hybrid Boolean processor-FPGA hardware emulation platform aiming to overcome these shortcomings. Sphinx hardware is a new hybrid architecture that integrates software programmable Boolean processors and FPGAs. Sphinx software is a compilation framework that conducts incremental design partitioning and implements the design-under-test components on Boolean processors and the rest on FPGAs. Together, Sphinx enables an incremental emulation flow and demonstrates high emulation performance, fast compile turnarounds, and good debuggability.

The time division multiplexing technique overcomes the bandwidth limitation by allowing FPGA chips to transmit multiple signals the maximum clocking frequency. With the additional multiplexers, this technique dramatically increases system-level routing capability in the FPGA-based emulator. However, the large number of virtual wires in the chip interconnection may impact emulation performance. The system-level FPGA routing tends to connect all virtual wires (signals) and considers emulation performance. At the same time, the challenge for system-level FPGA routing using time division multiplexing lies in the emulation performance.

Design rule check (DRC) violations after detailed routing prevent a design from being taped out. To solve this problem, state-of-the-art commercial EDA tools global-route the design to produce a global-route congestion map; this map is used by the placer to optimize the placement of the design to reduce detailed-route DRC violations. However, in sub-14nm processes and beyond, DRCs arising from multiple patterning and pin-access constraints drastically weaken the correlation between global-route congestion and detailed-route DRC violations. Hence, the placer|based on the global-route congestion map|may leave too many detailed-route DRC violations to be fixed manually by designers. In this paper, we present a method that employs (1) machine-learning techniques to effectively predict detailed-route DRC violations after global routing and (2) detailed placement techniques to effectively reduce detailed-route DRC violations. We demonstrate on several layouts of a sub-14nm industrial design that this method predicts the locations of 74% of the detailed-route DRCs (with false positive prediction rate below 0.2%) and automatically reduces the number of detailed-route DRC violations by up to 5x. Whereas previous works on machine learning for routability [30] [4] have focused on routability prediction at the floorplanning and placement stages, ours is the first paper that not only predicts the actual locations of detailed-route DRC violations but furthermore optimizes the design to significantly reduce such violations.

It is a misperception that the Chinese have the same word for crisis as opportunity. Despite that, a technical crisis does present opportunities for researchers and practitioners to solve interesting problems. In this talk we point out two crises: interconnect and runtime, we enumerate interesting physical-synthesis problems arising from these crises, and we discuss the possibility of employing machine learning and hardware acceleration techniques to attack those problems.

In this paper, we propose a novel simulation algorithm for large scale structured power grid networks. The new method formulates the traditional linear system as a special two-dimension Poisson equation and solves it using an analytical expressions based on FFT technique. The computation complexity of the new algorithm is O(NlgN), which is much smaller than the traditional solver's complexity O(N1.5) for sparse matrices, such as the SuperLU solver and the PCG solver. Also, due to the special formulation, graphic process unit (GPU) can be explored to further speed up the algorithm. Experimental results show that the new algorithm is stable and can achieve 100X speed up on GPU over the widely used SuperLU solver with very little memory footprint.

Power and variation are the biggest concerns of physical design today. Clock distribution network is at the center of both the power and variation concerns. Clock distribution networks consume a lion's share of the total IC power consumption for two reasons. First, the clock distribution network requires many large buffers to deliver crisp clock signals across a large area of the IC. Second, the clock distribution network uses many small buffers to balance the clock skews. Clock distribution networks are also most susceptible to variation for two reasons. First, both the latency and length of a clock path are usually much longer than those of typical timing paths. Second, variations to clock path delays may have a 2X impact to the timing of a timing path. Let's consider a timing path between a launching and a capturing flop and suppose that the clock path to the launching flop is sped up by 100ps and the clock path to the capturing flop is slowed down by 100ps due to variation. The impact to the hold constraint of the timing path would be 200ps. Our customers have seen chip failures due to hold violations caused by variation in this manner. Therefore, for 45nm technology nodes and beyond, we believe that a power-efficient and variation-tolerant clock distribution network is a necessary condition for a competitive IC product. In this talk we discuss the industrial clock design problems, designers' strategies for resolving the problems and the capabilities of commercial tools that we must provide to support the designers.

In modern designs, the delay of a net can vary significantly depending on its routing. This large estimation error during the pre-routing stage can often mislead the optimization of the netlist. We extend state-of-the-art interconnect-driven physical synthesis by introducing a new paradigm (namely, persistence) that relies on guaranteed net routes for the most sensitive nets while performing circuit optimization in the pre-route stage. We implemented our proposed approach in a cutting-edge industrial physical synthesis flow; this involved the automatic identification and routing of critical nets that were likely to be mispredicted, the automatic update of their routes during the subsequent pre-routing stage optimizations, and the guaranteed retention of their routes across the routing stage. Our approach achieves significant performance improvements on a suite of real-world 65nm designs, while ensuring that the impact on their routability remains negligible. Furthermore, our experimental results scale very well with design size.

We present two techniques, (1) placement-based timing-driven partitioner (PTP) and (2) virtual physical synthesis based budgeter (VSB), that support effective distributed physical synthesis.

We present a method for using a set of temporal properties (SVA, PSL, OVA, RTL monitors) as environment models for industrial-strength hybrid verification that combines formal methods with constrained random simulation. We demonstrate the effectiveness of the method on real-world designs.

Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register clustering that reduces clock power by placing registers in the same leaf cluster of the clock trees in a smaller area and (2) activity-based net weighting that reduces net switching power by assigning a combination of activity and timing weights to the nets with higher switching rates or more critical timing. The method applies to designs with multiple clocks and gated clocks. We implemented the method and obtained experimental results on 8 real-world designs after placement, routing, extraction and analysis. The power-aware placement method achieved on average 25.3% and 11.4% reduction in net switching power and total power respectively, with 2.0% timing, 1.2% cell area and 11.5% runtime impact. This method has been incorporated into a commercial physical design tool.

We present a new abstraction refinement algorithm to better refine the abstract model for formal property verification. In previous work, refinements are selected either based on a set of counter examples of the current abstract model, as in [5][6][7][8][9][19][20], or independent of any counter examples, as in [17]. We (1) introduce a new "controllability" analysis that is independent of any particular counter examples, (2) apply a new "cooperativeness" analysis that extracts information from a particular set of counter examples and (3) combine both to better refine the abstract model. We implemented the algorithm and applied it to verify several real-world designs and properties. We compared the algorithm against the abstraction refinement algorithms in [19] and [20] and the interpolation-based reachability analysis in [14]. The experimental results indicate that the new algorithm outperforms the other three algorithms in terms of runtime, abstraction efficiency (as defined in [19]) and the number of proven properties.

We present RFN, a formal property verification tool based on abstraction refinement. Abstraction refinement is a strategy for property verification. It iteratively refines an abstract model to better approximate the behavior of the original design in the hope that the abstract model alone will provide enough evidence to prove or disprove the property.

We present Ketchum, a tool that was developed to improve the productivity of simulation-based functional verification by providing two capabilities: (1) automatic test generation and (2) unreachability analysis. Given a set of "interesting" signals in the design under test (DUT), automatic test generation creates input stimuli that drive the DUT through as many different combinations (called coverage states) of these signals as possible to thoroughly exercise the DUT. Unreachability analysis identifies as many unreachable coverage states as possible.

Although model checking is an exhaustive formal verification method, a bug can still escape detection if the erroneous behavior does not violate any verified property.We propose a coverage metric to estimate the "completeness" of a set of properties verified by model checking.A symbolic algorithm is presented to compute this metric for a subset of the CTL property specification language.It has the same order of computational complexity as a model checking algorithm.Our coverage estimator has been applied in the course of some real-world model checking projects.We uncovered several coverage holes including one that eventually led to the discovery of a bug that escaped the initial model checking effort.

We present an automated formal verification method that can detect common pipeline-control bugs of logic-design components containing thousands of registers. The method models logic designs using controlled token nets. A controlled token net consists of: a token net that models the data flow in the datapath using token semantics; a control logic that models the control machines using traditional finite state semantics. We provide algorithms to (1) extract a controlled token net from a logic design, (2) minimize the controlled token net, and (3) compute an abstract interpretation of the controlled token net for efficient model checking. We implemented and applied the method to 6 Intel logic-design components containing up to 4500 registers and successfully detected 8 pre-silicon errata. 1.1 Keywords Pipeline control verification, controlled token net, abstract interpretation, processor verification, model checking, formal verification, functional verification, computer-aided design 2.

Presents a model-checking procedure and its implementation for the automatic verification of embedded systems. The system components are described as hybrid automata-communicating machines with finite control and real-valued variables that represent continuous environment parameters such as time, pressure and temperature. The system requirements are specified in a temporal logic with stop-watches, and verified by symbolic fixpoint computation. The verification procedure-implemented in the Cornell Hybrid Technology tool, HyTech-applies to hybrid automata whose continuous dynamics is governed by linear constraints on the variables and their derivatives. We illustrate the method and the tool by checking safety, liveness, time-bounded and duration requirements of digital controllers, schedulers and distributed algorithms.

We describe a new implementation of HYTECH, a symbolic model checker for hybrid systems. Given a parametric description of an embedded system as a collection of communicating automata, HYTECH automatically computes the conditions on the parameters under which the system satisfies its safety and timing requirements. While the original HYTECH prototype was based on the symbolic algebra tool Mathematica, the new implementation is written in C++ and builds on geometric algorithms instead of formula manipulation. The new HYTECH offers a cleaner and more expressive input language, greater portability, superior performance (typically two to three orders of magnitude), and new features such as diagnostic error-trace generation. We illustrate the effectiveness of the new implementation by applying HYTECH to the automatic parametric analysis of the generic railroad crossing benchmark problem and to an active structure control algorithm.

We present a general framework for the formal specification and algorithmic analysis of hybrid systems. A hybrid system consists of a discrete program with an analog environment. We model hybrid systems as finite automata equipped with variables that evolve continuously with time according to dynamical laws. For verification purposes, we restrict ourselves to linear hybrid systems, where all variables follow piecewise-linear trajectories. We provide decidability and undecidability results for classes of linear hybrid systems, and we show that standard program-analysis techniques can be adapted to linear hybrid systems. In particular, we consider symbolic model-checking and minimization procedures that are based on the reachability analysis of an infinite state space. The procedures iteratively compute state sets that are definable as unions of convex polyhedra in multidimensional real space. We also present approximation techniques for dealing with systems for which the iterative procedures do not converge.

We present a model checking procedure and its implementation for the automatic verification of embedded systems. Systems are represented by hybrid automata - machines with finite control and real-valued variables modeling continuous environment parameters such as time, pressure, and temperature. System properties are specified in a real-time temporal logic and verified by symbolic computation. The verification procedure, implemented in Mathematica, is used to prove digital controllers and distributed algorithms correct. The verifier checks safety, liveness, time-bounded, and duration properties of hybrid automata.>

A set of vertices D is a dominating set of a graph $G = ( V,E )$ if every vertex in $V - D$ is adjacent to a vertex in D. The domatic number $d ( G )$ of a graph $G = ( V,E )$ is the maximum number k such that V can be partitioned into k disjoint dominating sets $D_1 , \cdots ,D_k $. The main purpose of this paper is to give linear algorithms for the domatic number problem in interval graphs. This paper also proves that $d ( G ) = \delta ( G ) + 1$ for any interval graph G, where $\delta ( G )$ is the minimum degree of a vertex in G.