Demo Data from EDBT 2026 / reviewers in the wild / expert
Koichiro Ishihara
dblp:15/849
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 1986
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 2 | 1986 | Incremental logic synthesis through gate logic structure identification · DAC 1986 Polaris: Polarity propagation algorithm for combinational logic synthesis · DAC 1984 |
Electronic design automation › logic synthesis
incremental synthesis |
0.0 | 1 | 1986 | Incremental logic synthesis through gate logic structure identification · DAC 1986 |
Electronic design automation › logic synthesis
combinational logic synthesis |
0.0 | 1 | 1984 | Polaris: Polarity propagation algorithm for combinational logic synthesis · DAC 1984 |
Electronic design automation
physical design |
0.0 | 1 | 1986 | Incremental logic synthesis through gate logic structure identification · DAC 1986 |
Methods — techniques the papers use, named apart from their topics
gate matrix method · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1986 | Incremental logic synthesis through gate logic structure identificationabstractThis paper describes incremental logic synthesis for supporting function logic changes in the physical design stage of digital systems. The incremental logic synthesis is distinguished from logic synthesis in the respect that it updates only gate logic components, which must be changed due to the function logic changes, in the physically optimized gate logic structure. For making the incremental logic synthesis feasible, a gate logic structure identification and editing system has been developed with a corresponding gate matrix method as its core. This system has greatly contributed to the increase in design efficiency of the very large computer series M68XH. T. Shinsha, T. Kubo, Y. Sakataya, J. Koshishita, Koichiro Ishihara |
DAC | 5 |
| 1984 | A Proper Treatmemt Of Syntax And Semantics In Machine TranslationabstractA proper treatment of syntax and semantics in machine translation is introduced and discussed from the empirical viewpoint. For English-Japanese machine translation, the syntax directed approach is effective where the Heuristic Parsing Model (HPM) and the Syntactic Role System Play important roles. For Japanese-English translation, the semantics directed approach is powerful where the Conceptual Dependency Diagram (CDD) and the Augmented Case Marker System (which is a kind of Semantic Role System) play essential roles. Some examples of the difference between Japanese sentence structure and English sentence structure, which is vital to machine translation, are also discussed together with various interesting ambiguities. Yoshihiko Nitta, Atsushi Okajima, Hiroyuki Kaji, Youichi Hidano, Koichiro Ishihara |
COLING | 5 |
| 1984 | Polaris: Polarity propagation algorithm for combinational logic synthesis
T. Shinsha, T. Kubo, M. Hikosaka, K. Akiyama, Koichiro Ishihara |
DAC | 5 |
| 1982 | A Heuristic Approach To English-Into-Japanese Machine Translation
Yoshihiko Nitta, Atsushi Okajima, Fumiyuki Yamano, Koichiro Ishihara |
COLING | 4 |