Forsilicon carbide (SiC) MOSFET applications, it has been a constant challenge to address the trade-off among drain-source voltage slew rate (dv${}_{\mathbf {ds}}$/dt), drain-source voltage spike, and turn-off loss. The existing active gate drivers (AGDs) have not considered the influence of dynamically varying drain current, resulting in increased turn-off loss and voltage spike. To address this issue, this paper proposes a cross-cycle dynamic active gate driver (CDAGD) that features constant (dv${}_{\mathbf {ds}}$/dt)${}_{\mathbf {max}}$and spike under dynamic drain current. By deriving the quantitative relationship among the gate current,drain current, (dv${}_{\mathbf {ds}}$/dt)${}_{\mathbf {max}}$, and voltage spike, the optimal gate currents in different switching stages are determined. Furthermore, the CDAGD incorporates a cross-cycle gate current regulator (CCGCR) to generate the required gate currents in different stages, and a dynamic switching timing controller (DSTC) to locate the optimal timing of the stages. With the CDAGD providing the optimal gate current, the turn-off loss is minimized with reduceddv${}_{\mathbf {ds}}$/dtand spike.Fabricated in a$0.18\mu $m BCD process, the CDAGD chip achieves a maximum reduction in turn-off loss of 72.2% and 37.9% compared with the conventional gate driver (CGD) and AGD under varying drain current. A 45.9% reduction in turn-off time is also achieved with the proposed gate driver.