Performance degradation and higher power dissipation for data-intensive applications are common in von Neumann computers. This is due to the data transfer between the memory and processor. Non-von Neumann architecture addresses this issue by performing computations within the memory, that is, in-memory computing. The nonvolatile memory can be built using an alternative building block called a memristor. Logical NOT and NOR gates can be realized on memristor crossbars. This allows to perform arithmetic and logic operations within the memory. An architectural support for a constant time in-memory comparison has been introduced. This adds FILL and MCMP instructions to the instruction set. Four basic set operations are implemented using the instruction set. In-memory union, cartesian product, transitive closure, and power set generation achieve an average energy reduction of$168\times $,$249\times $,$134\times $, and$264\times $, respectively. However, for higher input sizes, central processing unit-based union, cartesian product, and transitive closure perform better by an average of$1.58\times $,$1.23\times $, and$2.07\times $, respectively. In-memory power set generation achieves an average speed-up of$1.14\times $.

Summary Digital microfluidic biochips (DMFBs) are designed to efficiently carry out biochemical and biomedical analysis in a miniaturized way. DMFBs offer various advantages over traditional laboratory techniques and reduces cost, and increases automation and software programmability. Scheduling of microfluidic operations is the first and essential step in the fluidic‐level synthesis of DMFBs, while the other two are the module placement and droplet routing. Scheduling DMFB operations is a multiconstrained optimization problem, and the particular decision problem is NP‐complete. We propose a hybrid artificial bee colony (ABC) algorithm using generalized N‐point crossover (GNX) based scheduling of DMFB operations. Proposed ABC‐GNX perturbs through search space, evaluates various schedules possible, and returns the best schedule among the evaluated schedules. Simple list scheduling based heuristic algorithms can explore a single schedule based on the sequence generated by the priority function. Iterative improvement based search algorithms explore the search space and evaluate more schedules, but the proposed ABC‐GNX algorithm produces optimal solutions in shorter execution times. Simulation results show that the proposed ABC‐GNX produces a higher number of optimal completion times and faster execution times than existing algorithms.

The present work introduces a hardware based technique for reduction of in-rush current in processors with power gating (PG) facility. A PG instruction has been introduced which is responsible in turning on multiple components from sleep to active mode at overlapped time intervals. The supporting hardware for the proposed PG instruction allows overlapped wake-up as long as the resultant in-rush current is tolerable by the system. The efficacy of the proposed method is evaluated on MiBench and MediaBench benchmark programs. The proposed method reduces in-rush current by an average of 35% with average performance loss of 5%.

The in-rush current due to wake-up of power gating (PG) components causes faster discharge of battery. This work introduces an instruction controlled hybrid battery-supercapacitor (B-SC) system for longer battery life in systems with instruction controlled PG. Two instructions have been introduced along with architectural support. The first instruction disconnects the battery from the PG components if the charge in the supercapacitor greater than or equal to the charge required by wake-up of PG components. The other instruction connects the battery to the PG components for recharging the supercapacitor. Disconnecting the battery during wake-up minimizes rate capacity effect (C-rate) for longer battery life. An algorithm is designed to schedule the proposed battery control instructions within a program having PG instructions. The efficacy of the proposed method is evaluated on MiBench and MediaBench benchmark programs. The proposed method reduces C-rate by an average of 14.25% at the cost of average performance loss of 6.87%.