Physical Unclonable Functions (PUFs) are vital for secure hardware authentication due to their intrinsic uniqueness. RRAM-based PUFs offer advantages such as compactness, low power, and CMOS compatibility, but suffer from reliability issues under environmental stress such as temperature and aging. This work proposes a self-checking RRAM-based PUF architecture using a resistance-delay mapping method to generate reliability-quantified challenge-response pairs (CRPs). A configurable Delay Amplification Chain (DAC) converts device-to-device(D2D) resistance variations into measurable timing differences, ensuring stable operation from -55°C to 125°C and ± 10% VDD fluctuations. A built-in self-checking mechanism filters unstable CRPs via complementary delay biases during the dark bit filtration stage, reducing bit error rate (BER) from 5.2% to 0.77%. A hierarchical framework further classifies CRPs into 11 reliability levels, enabling adaptive key management. Implemented in 180nm CMOS/RRAM technology, the design achieves 49.61% inter-chip and 49.80% reconfig Hamming distances across 50 instances, showing strong uniqueness and reconfigurability. No BER degradation was found in 10-year aging simulations. The design meets NIST SP800-22 randomness standards and offers a scalable and entropy-aware solution for IoT security.

Montgomery Modular Multiplication (MMM) is widely used in many public key cryptography systems. This paper presents a Flexible Low Area-Latency MMM (FLALM) implementation, which supports Generic Montgomery Modular Multiplication (GMM) and Square Montgomery Modular Multiplication (SMM) operations. A new SMM schedule for the Finely Integrated Product Scanning (FIPS) GMM algorithm is proposed to accelerate SMM with tiny additional design. Furthermore, a new FIPS dual-schedule is proposed to solve the data hazards of this algorithm. Finally, we explore the trade-off between area and latency, and present the FLALM to accelerate GMM and SMM. The FLALM is implemented on FPGA (Virtex-7 platform). The results show that the area*latency (AL) value of FLALM (wordsize$w$=128) is 38.1% and 44.7% better than the previous state-of-art scalable references when performing 1024-bit and 2048-bit GMM, respectively. Moreover, when computing SMM, the advantage of AL value is raised to 73.7% and 86.3% respectively.

With the wide application of the Internet of Things technology, the hardware security has attracted more and more attention from users around the world. Hardware Trojan (HT) of integrated circuit (IC) has become a main security threat gradually. Therefore, HT detection is very significant. In this article, a HT automatic test system used for side-channel test combined logic test is constructed with a high-performance oscilloscope, FPGA chips, a NI digital acquisition card and LabVIEW software. Besides, the test flow chart and data processing method are depicted in detail. Spectral feature analysis combined principal component analysis is proposed for feature extraction. Fuzzy C-means clustering combined spectral energy analysis is put forward to distinguish the Trojan category from the golden category. Then Fusion distance (i.e. Mahalanobis distance combined Euclidean distance) is presented for the real-time HT recognition. A 128-bit AES cipher circuit and a 2-bit counter are applied as a golden circuit and a Trojan circuit, respectively. Experimental results demonstrate that the detection accuracy is 100% and the proposed detection method can easily achieve 0.1% HT detection sensitivity, which verifies that the detection method is feasible and effective.

Radio frequency identification technology (RFID) has empowered a wide variety of automation industries, such as logistics and freight transportation. To further promote RFID tags adoption, security, power consumption, and cost have always been issues of general concern. This article presents the first synergy of the RFID tag with embedded resistive RAM (RRAM) array and RRAM-based reconfigurable strong physical unclonable function (R-SPUF). The RRAM not only meets the mass storage and technology downscaling but also renders the ultralow-cost “1-cent RFID tag” more feasible. Moreover, the R-SPUF facilitates multiple initializations until a satisfactory distribution and has strong secure keys benefiting from its reconfigurability that improves both safety and reliability. The complete system operates at 13.56 MHz and is compliant with the ISO14443-A and ISO10373-6 (test) protocols. The RFID tag was fabricated on a 1.1-mm2 die based on the 0.18-$\mu \text{m}$CMOS process. Without resorting to the charge pumps for RRAM read–write operations, the total power consumption is as low as 52.3$\mu \text{W}$, of which the RRAM dissipates$16.2~\mu \text{W}$under a wireless power supply.