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Zekun Li 0005

dblp:150/2008-5 · DBLP profile ↗
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3ranked-venue papers
0as first author
3since 2021 · last 2025
0000-0003-1763-7190ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%
Computer networks
1 paper
Physical-layer communications · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › radio-frequency circuit design
millimeter-wave transceiver
0.912025
A 285-310 GHz four-channel transceiver with 22.6 dBm EIRP supporting 64QAM modulation in 130-nm SiGe process · Sci. China Inf. Sci. 2025
Integrated circuit design › radio-frequency circuit design
radio frequency integrated circuits
0.912025
A 285-310 GHz four-channel transceiver with 22.6 dBm EIRP supporting 64QAM modulation in 130-nm SiGe process · Sci. China Inf. Sci. 2025
Physical-layer communications
modulation
0.312025
A 285-310 GHz four-channel transceiver with 22.6 dBm EIRP supporting 64QAM modulation in 130-nm SiGe process · Sci. China Inf. Sci. 2025
YearPublicationVenuePosition
2025 A 285-310 GHz four-channel transceiver with 22.6 dBm EIRP supporting 64QAM modulation in 130-nm SiGe process
Si-Yuan Tang, Zekun Li 0005, Sidou Zheng, Dawei Tang, Jiayang Yu, Rui Zhou 0016, Chen-Yu Ding, Peigen Zhou, Zhe Chen 0021, Pinpin Yan, Jixin Chen, Wei Hong 0002
Sci. China Inf. Sci.2
2025 A 24-29.5-GHz Scalable 2 × 2 I-Q TX/RX Chipset With Streamlined IF Interfaces for DBF Systems
abstract
This paper proposes a 24-29.5 GHz$2\times 2$transmitter (TX) and receiver (RX) front-end chipset with streamlined intermediate frequency (IF) interfaces for digital beamforming (DBF) systems. An ultra-compact 90° coupler employing a three-dimensional (3-D) coupling structure achieves a 70% reduction in size compared to typical Lange couplers while maintaining excellent performance. This 3-D 90° coupler enables the synthesis/distribution of IF I-Q signals within the transceiver (TRX), enhancing the feasibility of mmWave DBF by reducing the demand for baseband channels and facilitating scalability for multi-beam arrays. To ensure a low-level error vector magnitude (EVM) in the TRX, the chipset employs joint package design for optimal power and noise performance. It utilizes an image-reject mixer to suppress RX image noise and introduces a DC-offset in the single-sideband up-converter for LO leakage regulation. Additionally, a frequency doubler chain is incorporated to enhance phase noise performance. Fabricated using 0.13-$\mu $m SiGe BiCMOS technology and packaged in WLCSP process, the TX achieves an average output 1-dB compression point ($OP_{1dB}$) of 20 dBm per channel. The RX chip features a minimum noise figure (NF) of 3.4 dB. Over-the-air (OTA) measurements conducted over a 1.1-m distance reveal a transmission data rate of up to 8 Gb/s using 16-QAM modulation at 25 GHz. Furthermore, when employing a 400-MHz 64-QAM 5G New Radio (NR) modulation, the system maintains EVM levels below -33 dB at 25 GHz and below -30 dB over 24-29.5 GHz.
Jixin Chen, Zhe Chen 0021, Xiaoyue Xia, Yun Hu 0005, Sidou Zheng, Zekun Li 0005, Rui Zhou 0016, Peigen Zhou, Wei Hong 0002
IEEE Trans. Circuits Syst. I Regul. Pap.7
2024 A 94-GHz 16T1R Hybrid Integrated Phased Array With ±50° Scanning Range for High-Date-Rate Communication
abstract
This article presents a fully packaged 94-GHz 16-channel local oscillator (LO) phase-shifting transmitter (TX) and a single-channel receiver (RX). The implementation is accomplished using a hybrid integration scheme, combining high-output-power 100 nm GaAs pHEMT front-end chips and highly-integrated 130 nm SiGe BiCMOS beamformer chips. High-accuracy LO phase shifting is achieved with the utilization of a commercial SiGe-based four-channel beamformer chips, offering 7-bit phase control at 24–28 GHz. A 26-to-78 GHz tripler chain using power-enhancing and harmonic-suppression techniques, a 16-to-94 GHz bi-directional mixer, and a 94-GHz power amplifier are designed in the transmitter front-end chip based on the GaAs process. The GaAs transmitter front-ends are wire-bonded to microstrip lines and then converted to low-loss substrate integrated waveguides (SIWs), which directly feed a high-gain TEM horn antenna array. The inter-element spacing of the transmitter array is optimized to 1.6 mm ($0.5 \lambda _{0}$@94 GHz) for a wide scanning range. The 16-channel transmitter achieves a wide scanning range of ±50° and a peak effective isotropic radiated power (EIRP) of 43.6 dBm at 94 GHz. The GaAs receiver chip is packaged with the WR10 waveguide RF interface and connected to a horn antenna. The packaged GaAs receiver module achieves a conversion gain (CG) of 25 dB and a noise figure (NF) of 5.8 dB. Additionally, the 16T1R over-the-air (OTA) measurement supports 5G New Radio 400-MHz 64-QAM signal between 88 and 94 GHz over a 5-meter ±48° scanning range.
Sidou Zheng, Xiaoyue Xia, Si-Yuan Tang, Zekun Li 0005, Rui Zhou 0016, Peigen Zhou, Debin Hou, Jixin Chen, Wei Hong 0002
IEEE Trans. Circuits Syst. I Regul. Pap.5