Yibai He

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3ranked-venue papers

1as first author

1since 2021 · last 2025

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2 · 1 first-authorSystems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

2 papers

Hardware reliability and fault tolerance · 77% Integrated circuit design · 23%

Topics — the 5 heaviest of 5, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Hardware reliability and fault tolerance soft errors	0.4	2	2015	Flip-flops soft error rate evaluation approach considering internal single-event transient · Sci. China Inf. Sci. 2015 Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology · Sci. China Inf. Sci. 2014
Hardware reliability and fault tolerance › soft errors single event transient	0.2	1	2015	Flip-flops soft error rate evaluation approach considering internal single-event transient · Sci. China Inf. Sci. 2015
Hardware reliability and fault tolerance › soft errors single-event upset	0.2	1	2014	Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology · Sci. China Inf. Sci. 2014
Integrated circuit design digital circuit design	0.1	2	2015	Flip-flops soft error rate evaluation approach considering internal single-event transient · Sci. China Inf. Sci. 2015 Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology · Sci. China Inf. Sci. 2014
Integrated circuit design › digital circuit design › sequential circuit design flip-flop	0.1	2	2015	Flip-flops soft error rate evaluation approach considering internal single-event transient · Sci. China Inf. Sci. 2015 Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology · Sci. China Inf. Sci. 2014

Methods — techniques the papers use, named apart from their topics

soft error rate evaluation · 0.2

Year	Publication	Venue	Position
2025	VPFU: A Bit-Serial Architecture for Energy-Efficient Acceleration of Ultra-low Precision DNNs Yibai He	ICA3PP (1)	2
2015	Flip-flops soft error rate evaluation approach considering internal single-event transient Ruiqiang Song, Shuming Chen, Yibai He, Yankang Du	Sci. China Inf. Sci.	3
2014	Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology Yibai He, Shuming Chen	Sci. China Inf. Sci.	1