Protein phosphorylation regulates protein function and cellular signaling pathways, and is strongly associated with diseases, including neurodegenerative disorders and cancer. Phosphorylation plays a critical role in regulating protein activity and cellular signaling by modulating protein-protein interactions (PPIs). It alters binding affinities and interaction networks, thereby influencing biological processes and maintaining cellular homeostasis. Experimental validation of these effects is labor-intensive and expensive, highlighting the need for efficient computational approaches. We propose DeepPhosPPI, the first sequence-based deep learning framework for phosphorylation effects on PPIs prediction, which employs the pre-trained protein language model for feature embedding, with ProtBERT and ESM-2 as alternative backbone encoders. By combining attention-based convolutional neural network and Transformer models, DeepPhosPPI accurately predicts phosphorylation effects. The experimental results show that DeepPhosPPI consistently outperforms state-of-the-art methods in multiple tasks, including functional sites identification and regulatory effect classification.

Controller area network (CAN) is widely adopted in automobiles and susceptible to cyber attacks with the development of intelligent connected vehicles. While neural networks have demonstrated high accuracy in detection of such attacks, they consume a large amount of resources, hence unsuitable to be directly used for the automotive domain. In this work, we propose a lightweight intrusion detection system (LIDS) for CAN. It first filters out denial-of-service (DoS) and Fuzzy attacks through list screening, following which, a multilayer perceptron (MLP) model is deployed to predict Impersonation attacks. Leveraging this combination, the detection accuracy is kept and the resources required are significantly reduced. LIDS is able to run on small hardware with 520-kB memory and CPU of 240 MHz. Its power consumption is one order of magnitude lower than the existing works, thus an excellent candidate for protection of CAN in automobiles.

As promising industrial embedded networks, Controller Area Networks with Flexible Data-rate (CAN-FD) are widely used in time-sensitive domains, such as automotive networks. However, the absence of built-in security mechanisms in CAN-FD necessitates the development of security protection mechanisms. The existing Lightweight Authentication for Secure Automotive Networks (LASAN) framework focuses on enhancing the security of CAN/CAN-FD communication but neglects the conflict between security and delay. In this study, we conduct a thorough analysis of the causal mechanism related to the security and delay of LASAN and propose a static message scheduling method called Cooperative Swapping Approach (CSA) to achieve secure and low-delay CAN-FD communication. CSA is to minimize the end-to-end delay of precedence-constrained CAN-FD applications by swapping message positions in a valid message sequence. Nevertheless, exchanging message positions may impact the precedence dependencies between messages; therefore, we propose a novel Cooperative Transform Approach (CTA) within the CSA to efficiently preserve these precedence constraints. Valid message sequences with minimal end-to-end delays of a motivation example and an Adaptive Cruise Control (ACC) application are obtained in LASAN by CSA. These sequences are implemented on the embedded microcontroller platform of STM32H743IITs for evaluation. Experimental results show that our proposed CSA can effectively reduce the end-to-end delay of LASAN and outperform the state-of-the-art static message scheduling method in terms of low delay.

Multiple processors system on chip (MPSoC) has been the trend in cyber-physical systems (CPSs), and reasonable partitioning for MPSoC resources is a critical step in CPSs design. The uncertainties of environment and time are both important factors that need to be considered in the design, but none of the previous work pays attention to two uncertainties at the same time. The state-of-the-art work presented a detailed process of applying uncertain programming to solve the partitioning problem, which provides a solution for designing in an uncertain environment. However, this work only considers the bipartition scenario which cannot be directly applied to MPSoC, and it does not focus specifically on time uncertainty. In this paper, we propose a method for modeling the MPSoC partitioning problem in an uncertain environment, with the time uncertainty concern. We present the uncertain model that can be applied to the multiple optional resources scenario. We build the optimization model with the objective of minimizing time, analyze two different cases of minimizing the uncertain time, and finally prove a unified deterministic model to solve. We come up with three algorithms, including the heuristic algorithm, the genetic algorithm, and the exact algorithm, and experiments show that the heuristic algorithm and the genetic algorithm can obtain good approximate solutions compared with the exact algorithm.

Proteins commonly perform biological functions through protein-protein interactions (PPIs). The knowledge of PPI sites is imperative for the understanding of protein functions, disease mechanisms, and drug design. Traditional biological experimental methods for studying PPI sites still incur considerable drawbacks, including long experimental time and high labor costs. Therefore, many computational methods have been proposed for predicting PPI sites. However, achieving high prediction performance and overcoming severe data imbalance remain challenging issues. In this paper, we propose a new sequence-based deep learning model called CLPPIS (standing for CNN-LSTM ensemble based PPI Sites prediction). CLPPIS consists of CNN and LSTM components, which can capture spatial features and sequential features simultaneously. Further, it utilizes a novel feature group as input, which has 7 physicochemical, biophysical, and statistical properties. Besides, it adopts a batch-weighted loss function to reduce the interference of imbalance data. Our work suggests that the integration of protein spatial features and sequential features provides important information for PPI sites prediction. Evaluation on three public benchmark datasets shows that our CLPPIS model significantly outperforms existing state-of-the-art methods.

Intelligent connected vehicle is rapidly growing with the 5-G technology; the diversity of functional interfaces has significantly expanded the avenues of attack, making automotive controller area network (CAN) more vulnerable to cyberthreats. Automotive CAN network attacks are a direct threat to traffic safety, and in this study, we explore the use of intrusion detection techniques for mitigating cyberattacks. However, most automotive CAN network intrusion detection technologies are not capable of defending against sophisticated attacks, making it extremely challenging for detecting intrusions in practice. In this article, we propose a novel time interval conditional entropy method for detecting intrusions in automotive CAN networks. The time interval conditional entropy intrusion detection method is not susceptible to interference and is capable of detecting a variety of attacks. In our experiments, the conditional entropy values of regular communication messages are collected and utilized to distinguish and detect the attacks. The time interval conditional entropy detection method is implemented and evaluated in our controller area net-work bus (CAN-BUS) network platform. The experiments show that our method has higher detection accuracy and is easier to deploy compared to existing automotive CAN network intrusion detection methods.

Recent research has shown that collaborative computing of CPUs and GPUs in the same system can effectively accelerate large-scale SGD-based matrix factorization (MF), but it faces the problem of limited scalability due to parameter synchronization in the server. Theoretically, asynchronous methods can overcome this shortcoming. However, through a series of tests, observations, and analyses, we realize that developing an effective asynchronous multi-CPU/GPU MF framework faces several major design challenges: the underutilized CPUs, high communication overhead, and the asynchronous data safety issue. This article presents a unified multi-CPU/GPU asynchronous computing framework for SGD-based matrix factorization, namedUMA-MF.UMA-MFtreats CPUs and GPUs in the system as distributed workers that train matrix datasets in parallel and update feature parameters asynchronously. It provides a cache-friendly CPU external working mode, which can improve the CPU's cache hit rate, thereby promoting the efficient use of CPUs. It offers an algorithm to find the shortest communication ring topology of heterogeneous CPU/GPU workers and builds computing-communication pipelines to minimize the communication overhead. It implements a wait-free structure and load-balanced data distribution to achieve asynchronous data safety.UMA-MFcan effectively accelerate SGD-based MF on multi-CPU/GPU systems in an asynchronous way. On a physical platform with configurations ranging from single processor system to 2CPUs--4CPUs system, for five common datasets Netfix, R1, R2, Goodreads, and de-dense,UMA-MFachieves up to 3.56x speedup compared with HCC-MF, which is the state-of-the-art multi-CPU/GPU synchronous computing framework for SGD-based MF.UMA-MFalso shows good scalability. When the system is scaled to 2CPUs-4GPUs, the training time speedup ofUMA-MFcan reach 70%--97% of the ideal speedup.

Controller area network with flexible data-rate (CAN-FD) has received great attention in automotive cyber–physical systems (ACPSs) due to its high bandwidth and long payload. However, CAN-FD adopts a broadcast message transmission mechanism and lacks security protection, making it extremely vulnerable to cyberattacks. CAN-FD message packing (packing signals into messages) with low bandwidth occupancy (utilization) under security constraints is the prerequisite for running intelligent applications in ACPS. In this work, we implement a two-stage CAN-FD message packing solution to reduce bandwidth utilization and improve signal acceptance rate under security constraints. The first stage solves the message packing problem of minimizing bus bandwidth utilization under security constraints. The second stage aims at improving the signal acceptance rate by repacking signals. Experimental results show that the first stage reduces average bus bandwidth utilization by 135% compared with the unpacking solution, and the second stage improves the average signal acceptance rate by 5% than existing advanced methods.

This paper presents a heterogeneous collaborative computing framework for SGD-based Matrix Factorization, named HCC-MF. HCC-MF can train the feature matrix efficiently using multiple CPUs and GPUs. It performs collaborative computing with data parallelism, where a server CPU is in charge of management and synchronization and other heterogeneous worker CPUs and worker GPUs performs calculation with their data assignments. HCC-MF adopts two data partition strategies, “data partition with heterogeneous load balance” and “data partition with hidden synchronization.” We build a time cost model to guide the data distribution among multiple workers and we design several communication optimization techniques with consideration of datasets’ and processors’ characteristics. Experimental results indicate that HCC-MF can utilize more than 88% of the platform’s computing power, yielding a speedup of 2.9 compared with advanced SGD-based MF, CuMF_SGD, on large-scale data sets.

Summary Modern software development for services computing and cloud computing software systems is no longer based on a single database but on existing multidatabases and this convergence needs new software architecture and framework design. Most current popular frameworks are not designed for multidatabases, and many practical problems in development arise. This study designs and implements a software development framework called Java data access service (JDAS) for multidatabases using the object‐oriented programming language Java. The JDAS framework solves related problems that arise when other frameworks are employed in practical software development with multidatabases by presenting and introducing design methods. JDAS consists of the modules of the database abstract, object relational mapping, connection pools management, configuration management, data access service, and inversion of control. Results and case study reveal that the JDAS framework effectively reduces development complexity and improves development efficiency of the software systems with multidatabases. Copyright © 2017 John Wiley & Sons, Ltd.

ISO 26262 is a functional safety standard specifically made for automotive systems, in which the automotive safety integrity level (ASIL) is the representation of the criticality level. Recently, most studies have used ASIL decomposition to reduce the development cost of automotive functions. However, these studies have not paid special attention to the problem that the reliability goal may not be satisfied when ASIL decomposition is performed. In this study, we solve the problem of minimizing the development cost of a distributed automotive function while satisfying its reliability goal during the design phase by presenting two heuristic algorithms, reliabilitycalculation of scheme (RCS) and minimizing development cost with reliability goal (MDCRG). We first use RCS to calculate the reliability value of each ASIL decomposition scheme; then, the MDCRG is used to select the scheme with the minimum development cost while satisfying the reliability goal. Real-life benchmark and simulated functions based on real parameter values are used in experiments, and results show the effectiveness of the proposed algorithms.

Summary Parallel file systems commonly distribute a file across multiple file servers with a fixed‐size stripe, thereby allowing data access through multiple file servers. This default data layout works well in traditional homogeneous storage systems, but when solid state disks (SSDs) are conducted into a storage system, the data layout of hybrid parallel file systems has a chance to obtain better I/O performance. In this study, we propose a variable‐sized stripe level data layout strategy for hybrid parallel file systems (SLDP). SLDP divides the file into several regions according to the data access pattern and then finds the optimal configurations for each region among the solid state disk file server nodes and mechanical hard disk drive file server nodes. It uses variable stripe sizes to reorganize the data layout of file systems. Furthermore, it considers SSD space limitation, the main idea is to distribute key regions of the file to hybrid parallel file systems based on the optimal stripe configuration, which can significantly improve the system I/O throughput performance. The remaining parts of a file are then distributed according to the SSD free space threshold, which can leverage the SSD servers as much as possible. To achieve this, SLDP divides a large file into many fine‐grained regions and adjusts the data layout method for each region according to the access patter. Experimental results show that the SLDP is feasible and can improve system performance. Copyright © 2016 John Wiley & Sons, Ltd.

Heterogeneous processors are increasingly being used in embedded systems where parallel applications with precedence-constrained tasks widely exist. Reliability is an important functional safety requirement and reliability goal should be satisfied for safety-critical parallel applications; meanwhile, resource is limited in embedded systems and it should be minimized. This study solves the problem of resource consumption cost minimization of a reliable parallel application on heterogeneous embedded systems without using fault tolerance. The problem is decomposed into two subproblems, namely, satisfying reliability goal and minimizing resource consumption cost. The first subproblem is solved by transferring the reliability goal of the application to that of each task, and the second subproblem is solved by heuristically assigning each task to the processor with the minimum resource consumption cost while satisfying its reliability goal. Experiments with real parallel applications verify that the proposed algorithm obtains minimum resource consumption costs compared with the state-of-the-art algorithms.

The problem of minimizing the energy consumption of a real-time parallel application on a heterogeneous system has been studied recently, and slack time reclamation based on the dynamic voltage and frequency scaling (DVFS) energy-efficient design technique has been proposed as a solution. However, the state-of-the-art algorithms merely minimize energy consumption through an “upward” approach (i.e., from exit to entry tasks) and do not apply the “downward” approach (i.e., from entry to exit tasks) to energy consumption minimization. This study solves the same problem by employing “downward” and “upward” approaches. The concepts of deadline-slack and task level are introduced to transfer the deadline of the parallel application to each task, that is, “downward” energy consumption minimization is implemented. “Upward” energy consumption minimization by reclaiming the slack time is then included to implement “downward” and “upward” energy consumption minimization with low time complexity. Results of the experiments using real parallel applications show that the proposed algorithm can generate the minimum energy consumption compared with the state-of-the-art algorithms under different real-time and scale conditions.