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Pekka Enberg

dblp:150/5160 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2019
0000-0002-5661-2124ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Computer networks · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Operating systems · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Cloud and datacenter computing · 50% High-performance computing · 50%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing
lightweight operating system
0.112014
OSv - Optimizing the Operating System for Virtual Machines · USENIX ATC 2014
Cloud and datacenter computing
virtualization
0.112014
OSv - Optimizing the Operating System for Virtual Machines · USENIX ATC 2014

Methods — techniques the papers use, named apart from their topics

virtualization · 0.4OS optimization · 0.4
YearPublicationVenuePosition
2019 The Impact of Thread-Per-Core Architecture on Application Tail Latency
abstract
The response time of an online service depends on the tail latency of a few of the applications it invokes in parallel to satisfy the requests. The individual applications are composed of one or more threads to fully utilize the available CPU cores, but this approach can incur serious overheads. The thread-per-core architecture has emerged to reduce these overheads, but it also has its challenges from thread synchronization and OS interfaces. Applications can mitigate both issues with different techniques, but their impact on application tail latency is an open question. We measure the impact of thread-per-core architecture on application tail latency by implementing a key-value store that uses application-level partitioning, and inter-thread messaging and compare its tail latency to Memcached which uses a traditional key-value store design. We show in an experimental evaluation that our approach reduces tail latency by up to 71 % compared to baseline Memcached running on commodity hardware and Linux. However, we observe that the thread-per-core approach is held back by request steering and OS interfaces, and it could be further improved with NIC hardware offload.
Pekka Enberg, Ashwin Rao, Sasu Tarkoma
ANCS1
2019 I/O Is Faster Than the CPU: Let's Partition Resources and Eliminate (Most) OS Abstractions
abstract
I/O is getting faster in servers that have fast programmable NICs and non-volatile main memory operating close to the speed of DRAM, but single-threaded CPU speeds have stagnated. Applications cannot take advantage of modern hardware capabilities when using interfaces built around abstractions that assume I/O to be slow. We therefore propose a structure for an OS called parakernel, which eliminates most OS abstractions and provides interfaces for applications to leverage the full potential of the underlying hardware. The parakernel facilitates application-level parallelism by securely partitioning the resources and multiplexing only those resources that are not partitioned.
Pekka Enberg, Ashwin Rao, Sasu Tarkoma
HotOS1
2014 OSv - Optimizing the Operating System for Virtual Machines
Avi Kivity, Dor Laor, Glauber Costa, Pekka Enberg, Nadav Har'El, Don Marti, Vlad Zolotarov
USENIX ATC4