The demand for virtual private networks (VPNs) that provide confidentiality, integrity, and authenticity of communications is growing every year. IPsec is one of the oldest and most widely used VPN protocols, implemented between the internet protocol (IP) layer and the data link layer of the Linux kernel. This implementation method, known as bump-in-the-stack, has the advantage of being able to transparently apply IPsec to traffic without changing the application. However, its throughput efficiency (Gbps/core) is worse than regular Linux communication. Therefore, we chose the bump-in-the-wire (BITW) architecture, which handles IPsec in hardware separate from the host. Our proposed BITW architecture consists of inline cryptographic accelerators implemented in field-programmable gate arrays and a programmable switch that connects multiple such accelerators. A VPN gateway implemented with our architecture is transparent and improves the throughput efficiency by 3.51 times and power efficiency by 3.40 times over a VPN gateway implemented in the Linux kernel. It also demonstrates excellent scalability, and has been confirmed to scale to a maximum of 386.24 Gbps per tunnel, exceeding state-of-the-art technology in maximum throughput and efficiency per tunnel. In multiple-tunnels use cases, the proposed architecture improves the energy efficiency by 2.49 times.

Recently, computing systems have comprised specialized computing components such as FPGAs, GPUs, and various ASIC accelerators to enhance efficiency and performance. We proposed a queue structure mechanism to communicate between CPUs-FPGAs and offload tasks onto FPGAs asynchronously. This paper presents an FPGA system with a low latency autonomous DMA engine to enhance efficiency and performance. We build the system installed in eight FPGAs in which a customized DMA engine is implemented and evaluate communication performance including Software Stack for a single FPGA and the communication latency of an FPGA chain. In a single FPGA, our system achieves DMA read bandwidth of up to 68.5% and DMA write bandwidth of up to 62.2% for PCIe Gen3 x16 theoretical performance. An FPGA chain of up to 8 FPGAs in 4MB data size has latency of 3.7 milliseconds, which under half that when using the existing DMA method(7.6 milliseconds).

VTA-NIC Chip ArchitectureWe aim to achieve DL inference serving (DLIS) without CPU interference.We integrate hardware data paths as a NIC (Network Interface Card), a REST API parser/deparser and multiple VTAs (Versatile Tensor Accelerators).ConfigurationVTA-NICProcess node16 nm FinFET @Xilinx FPGANumber of Cores8 VTA CoresCore Frequency213 MHzMACs per core169Memory Throughput19.2GB/s (DDR4-2400)Number precisionINT8PerformancePower EfficiencyThe DLIS power efficiency of VTA-NIC is 6.1x better than that of GPU (Nvidia V100).Tail LatencyAt high load, the tail latency of heterogeneous systems unexpectedly increases. With our chip, the tail latency is predictable since it is proportional to the load.BackgroundRecently, web applications are often built on microservices.DL Inference Serving (DLIS) is one of those microservices1.DLIS is provisioned with a special accelerator instance2.The microservices/instances are loosely coupled via APIs.BackgroundAccelerator instances risk inefficient data movement.1.Moving data via host processors decreases the accelerator's utilization.3a.In our preliminary experiments, half of the DLIS latency was caused by moving data.2.Under high-load conditions, the interference of host processors degrades DLIS tail latency by up to 100 times4.a.In the real cloud, 9% of light DLIS tasks suffer server tail latency, and half of the serving time is waiting time.5Model: ResNet-18@TensorRTPrecision: INT8System: Triton Inference ServerAccelerator: Nvidia V100

Towards the deployment of flexible 5G mobile networks, this paper presents a hierarchical coordinated radio-resource scheduling method along with a scheme for its practical hardware implementation in a field-programmable gate array (FPGA). The scheduler in the 5G era will have to quickly perform coordinated scheduling for a huge number of transmission antennas and support flexibility for advanced scheduling algorithms. To meet these requirements, we designed an FPGA-based scheduler that hierarchically controls the radio transmissions of all transmission antennas beyond a central unit. Experimental measurements reveal that the FPGA-based hierarchical coordinated scheduler shows comparable processing speed on the radio-frame time scale. Moreover, in numerical simulations, the overall system throughput with the hierarchical coordinated scheduler is 1.25 times higher than that obtained by the conventional method when the number of transmission antennas and mobile terminals are 32 and 256, respectively. Our proposed scheduling method will enable the deployment of flexible 5G mobile networks.

This paper discusses a throughput enhancement technique for a coordinated radio-resource scheduler with a hardware accelerator in low-latency 5G mobile communications systems. In these 5G systems, the scheduler will have to search for the optimal combination of antennas and mobile terminals (MTs) from a huge number of possibilities within a sub-millisecond scheduling period. Without increasing the computational resource, it would be difficult to obtain the optimal combination when the number of accommodated MTs is large. To overcome this issue, the system throughput enhancement technique dynamically controls the search space on the basis of the number of MTs. This enables the scheduler to quickly approach the optimal combination under the computational resource constraint. Simulated results revealed that the scheduler with a hardware accelerator of 15.1 Mgates can search for the optimal combination that achieves higher system throughput within a 0.2-ms scheduling period. By dynamically controlling the search space, the scheduler performs effectively regardless of the number of MTs. The new scheduler will enable a practical future low-latency 5G system.

We propose a novel energy-efficient power saving technique coordinating CPEs via ONU. In addition, we first evaluate the proposal in a 10G-EPON system whose ONU sleep mechanism complies with IEEE Std. 1904.1 SIEPON and IEEE 802.3az EEE. It is revealed that the proposal yields ONU power savings of the order of 42 %. Moreover, it reduces the excessive latency by 40 % compared to unsynchronized power saving control.