This article proposes voltage ripple-based fault diagnosis of dc-link capacitors and fault-tolerant operation via power regulation in solid-state transformer (SST). An SST configured as an input-series-output-parallel (ISOP) structure generally consists of a cascaded multilevel H-bridge (CHB) converter and multiple isolated DC-DC converters. In a single-phase SST based on ISOP, the dc-link of the CHB exhibits second-order voltage ripples, which are inversely proportional to the dc-link capacitance. As capacitors age, their capacitance decreases, which is referred to as a capacitor fault. When a capacitor fault occurs in the dc-link, the voltage ripple can exceed the rated voltage of the capacitor, necessitating fault diagnosis and tolerant operation. In this article, by tracking the maximum and minimum of the dc-link voltage, the magnitude of the voltage ripple is compared to the value from the sound condition. This method allows for the diagnosis of the capacitor fault without additional circuits. Once the fault is diagnosed, the SST transitions to fault-tolerant operation. In this mode, the power of the faulty module is regulated to be lower than the others by adjusting the modulation of the CHB. As voltage ripples are proportional to their corresponding module powers, the reduction of voltage ripple in the faulty module becomes feasible. The validity of the proposed fault diagnosis and tolerant operation is verified through experimental and simulation results, respectively.

This article is a study of bidirectional DC/DC converter for the energy storage systems. Non-isolated interleaved bidirectional high step-up/down (NIBH) DC/DC converter consists of a coupled inductor and a switched capacitor. The NIBH converter has important features such as low ripple current on the low voltage side, low cost, low component count, high voltage conversion ratio, low voltage stress, and soft switching operation of switches. Two coupled inductors are connected in parallel to the low voltage side to have low ripple current and increase the turns ratio to achieve high step-up/step-down voltage gain. The switched capacitors can be stacked in series with the high voltage side to achieve high voltage gain, and the active clamp circuit enables the switches to reduce conduction and switching losses with low voltage stress and soft switching operation. To verify the theoretical analysis and performance of the proposed converter, a 650W prototype circuit was implemented in the laboratory.

This article proposes a current-prediction-based dead-time compensation technique designed to reduce zero-current-clamping in grid-connected cascaded H-bridge multilevel inverters (CHMI) using phase-shifted PWM (PS-PWM). In general, dead-time compensation is achieved by adding an offset voltage, derived from the voltage drop during dead-time. This offset voltage formula incorporates a polarity of grid current. However, when this polarity undergoes a transition within the control period, effective compensation is hindered, leading to the zero-current-clamping phenomenon. This effect is more pronounced in practical systems that utilize the shadow register function of a digital signal processor (DSP). In CHMI systems, particularly those with a lower switching frequency, current distortion becomes more prominent. In the proposed technique, the polarity ratio of the grid current reference during a control period is determined using current reference predictions, facilitating the generation of a precise offset voltage. Consequently, there is a notable attenuation of the odd-harmonic components intrinsic to the grid current, leading to a reduction of the zero-current-clamping phenomenon. The validity of this technique is demonstrated through simulation results based on a 7-level CHMI configuration.

This paper presents a method to increase the efficiency of the propulsion system through a synchronous pulse width modulation (synchronous PWM) pulse number selection method. In a propulsion system consisting of an inverter and a traction motor, the efficiency of inverter and the efficiency of traction motor are generally in a trade-off relationship depending on the switching frequency. Therefore, it is possible to adjust the efficiency of the inverter and efficiency of traction motor by using the synchronous PWM that can adjust the switching frequency. The proposal method produces a loss table by performing inverter and motor loss analysis on pulse numbers and selects pulse number that increase efficiency using the table. The validity of the proposed method was verified through simulation.

This paper proposes a modulation method to reduce power losses and achieve high efficiency for a single-phase NPC three-level inverter. In conventional switching methods, the bipolar and unipolar pulse width modulation methods are commonly used in a single phase inverter. However, these switching methods have the disadvantages in aspects of the power loss. The several clamp switching methods aggravating the Total Harmonic Distortion (THD) are introduced to solve the loss problem. To overcome these weaknesses in these switching methods, this paper proposes a novel clamp switching method that combines two switching method, unipolar PWM method and clamp switching method. Since the proposed method has all the advantages of both methods, the optimal performance in the power losses and THD can be obtained. The analysis of the power loss reduction and THD is showed through the simulation.