This study examines whether using stickers in workplace apologies effectively conveys the sender’s attitude and influences the receiver’s perception of justice, post-apology satisfaction, and trust. Adopting the receiver’s perspective, it investigates how different sticker types used across workplace communication directions (horizontal, downward, upward) affect fairness perceptions and the moderating role of the receiver’s gender. A 3 × 4 within-subjects design was employed (communication direction × sticker type: cute, ugly, formal, text-based), with 477 valid responses. Data were analyzed using ANOVA and linear regression. Results show that the interaction between communication direction and sticker type significantly influences perceptions of justice, which positively affects satisfaction and trust after the apology. The findings offer practical implications for LINE sticker creators and users, emphasizing the importance of choosing appropriate sticker types to enhance communication effectiveness. This study contributes to understanding workplace communication and offers strategies to foster better professional relationships through digital expression tools.

Real-world paintings are made, by artists, using brush strokes as the rendering primitive to depict semantic content. The bulk of the Neural Style Transfer (NST) is known transferring style using texture patches, not strokes. The output looks like the content image, but some are traced over using the style texture: it does not look painterly. We adopt a very different approach that uses strokes. Our contribution is to analyse paintings to learn stroke families-that is, distributions of strokes based on their shape (a dot, straight lines, curved arcs, etc.). When synthesising a new output, these distributions are sampled to ensure the output is painted with the correct style of stroke. Consequently, our output looks more "painterly" than NST output based on texture. Furthermore, where strokes are placed is an important contributing factor in determining output quality, and we have also addressed this aspect. Humans place strokes to emphasize salient semantically meaningful image content. Conventional NST uses a content loss premised on filter responses that is agnostic to salience. We show that replacing that loss with one based on the language-image model benefits the output through greater emphasis of salient content.

In this work, we propose a GPU-accelerated algorithm for frequent pattern(FP) mining without candidate generation. We observe that the existing FP-growth algorithm has critical characteristics unsuitable for GPU, including the tree data structure, deep recursion and heavy dynamic memory allocations. By utilizing iterative execution and collectively allocating memory on GPU, our proposed method significantly reduce the latency caused by large memory allocations of original FP-growth. Experiment results show that our solution outperforms baselines, including sequential FP-growth with CPU only and existing GPU-accelerated Apriori and FP-growth, on various data sets with a significant speedup, from several times to hundred times.

This work is motivated by the needs to synchronize task executions where tasks might use semaphores to protect their critical sections and run over accelerators. In particular, the Priority Ceiling Protocol is extended to manage priority inversion caused by accelerator usages. By recognizing the difference between an accelerator and a semaphore, higher-priority tasks are less likely blocked by lower-priority tasks, due to their requests for an accelerator. In particular, blocking that will not contribute to any deadlock and/or chained blocking is allowed in a managed way, with an objective to maximize the utilization of accelerators. A series of experiments is then conducted to derive insights to task synchronization when accelerators might be used.

This work is motivated by the advance of heterogeneous computing and the strong demands of workload acceleration in practice. By considering pipeline workloads over FPGA, this paper explores a systematic methodology to configure the hardware instances of each pipeline stage such that the maximum of the execution time of each stage is minimized, where the FPGA allocation with the memory bandwidth constraint is considered. For the target problem, an algorithm is proposed and proved being optimal, and a real implementation study is conducted. In the experimental results, an image filter FPGA implementation can outperform the CPU, GPU, and baseline FPGA solutions by 460%, 73%, and 1030%, respectively. Extensive simulations were also conducted with a large FPGA size to show the scalability of this work.