Convolutional neural networks (CNNs) have gained a massive impression in the fields of computer vision and especially in the embedded applications because of their high accuracy and performance. However, high computational complexity and power consumption due to convolution operations causes a high demand for low-power accelerators. A 3D geometric optimization strategy is proposed to alleviate the area and power requirements of Multiply Accumulate operations prevalent in all spatial CNNs. The proposed technique is generic and may be easily scaled for accelerators performing spatial 2D convolution.

Parallel computing is essential to achieve the manycore architecture performance potential, since it utilizes the parallel nature provided by the hardware for its computing. These applications will inevitably have to synchronize its parallel execution: for instance, broadcast operations for barrier synchronization. Conventional network-on-chip architectures for broadcast operations limit the performance as the synchronization is affected significantly due to the critical path communications that increase the network latency and degrade the performance drastically. A Wireless network-on-chip offers a promising solution to reduce the critical path communication bottlenecks of such conventional architectures by providing hardware broadcast support. We propose efficient barrier synchronization support using hybrid wireless/wired NoC to reduce the cost of broadcast operations. The proposed architecture reduces the barrier synchronization cost up to 42.79% regarding network latency and saves up to 42.65% communication energy consumption for a subset of applications from the PARSEC benchmark.

In this work, we introduce an hybrid WiNoC, which judicially uses the wired and wireless interconnects for broadcasting/multicasting of packets. A code division multiple access (CDMA) method is used to support multiple broadcast operations originating from multiple applications executed on the multiprocessor platform. The CDMA-based WiNoC is compared in terms of network latency and power consumption with wired-broadcast/multicast NoC.

Wireless Network-on-Chip (WNoC) has been proposed to overcome long-distance communication bottlenecks of wired NoCs. Token passing mechanism has generally been adapted to allocate the wireless channel among Wireless Interfaces (WIs). In this work, we propose a comparator based controller to provide a flexible and efficient channel allocation scheme. It utilizes a comparator attached to the antenna, along with modifications to header flit to perform channel allocation along with power gating WIs to save energy. Evaluation of proposed scheme on CPU/GPU system shows 53% reduction in token passes and 9% energy saving as compared to timer based approach.

Wireless Networks-on-Chip (WiNoC) are being explored for parallel applications to improve the performances by reducing the long distance/critical path communications. However, WiNoC still require precise propagation models to go beyond proof of concept and to demonstrate it can be considered as a realistic efficient alternative to wired NoC. In this paper, we present accurate 3D models based on measurements in Ka band and Electromagnetic (EM) simulations of transmission on silicon substrate in the V band and the Sub-THz band. Using these EM results, a time-domain simulation is performed using an On-Off Keying (OOK) modulation based transmission with different PA/LNA configurations. Our results highlight the type of performances and tradeoffs to be considered according to different parameters such as power output and amplifier's gain. By improving the knowledge about the signal propagation, one can conduct precise design space exploration for parallel applications. We discuss the realistic channel modeling and we present also hybrid solutions and associated limitations of WiNoC architectures. We conclude the paper with research directions to be explored to make WiNoC a reality.

Networks-on-Chip (NoCs) are fast becoming the de-facto communication infrastructures in chip multi-processors for large-scale applications. Wireless NoCs (WNoCs) offer a promising solution to reduce the long-distance communication bottlenecks of conventional NoCs by augmenting them with single hop, long-range wireless links. However, power consumption in routers and network elements still remains considerably high at ultra-deep submicron technologies. Analysis of network resources for several benchmarks shows that, utilization is application dependent and the desired performance can be achieved even without operating all resources at maximum specifications. In this work, we propose an energy-efficient WNoC architecture using Adaptive Multi-Voltage Scaling (AMS) to dynamically vary supply voltage for NoC routers and Wireless Interfaces (WIs) without adversely impacting performance. The proposed scheme uses a probabilistic model to predict router utilization during different application phases and scales voltage accordingly. It further reduces network energy by power-gating WIs that are not engaged in active communication to minimize their power consumption. We present detailed utilization estimation procedure, AMS control mechanism, and its hardware implementation. It saves up to 56 percent in network packet energy consumption and 62.50 percent power consumption in WIs for 256 core system as compared to baseline architectures without incurring significant performance penalty and area overheads.

The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of multi-hop links used in data exchange. To address these problems multi-hop wire interconnects in a NoC can be replaced with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers. Moreover, as it is an emerging technology, the on-chip wireless links also need to overcome significant challenges pertaining to reliable integration. In this paper we present various challenges and emerging solutions regarding the design of an efficient and reliable WiNoC architecture.