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Avik Bose

dblp:151/4571 · DBLP profile ↗
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3ranked-venue papers
3as first author
1since 2021 · last 2021
0000-0002-4592-4632ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorComputer networks · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 30% Embedded and real-time systems · 30% Reconfigurable computing and FPGAs · 30%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip
network topology
0.512021
Dynamic application mapping on CTH network: a performance-centric approach · SenSys 2021
Reconfigurable computing and FPGAs › application mapping
runtime application mapping
0.512021
Dynamic application mapping on CTH network: a performance-centric approach · SenSys 2021
Embedded and real-time systems › multicore real-time systems
task mapping and scheduling
0.512021
Dynamic application mapping on CTH network: a performance-centric approach · SenSys 2021

Methods — techniques the papers use, named apart from their topics

synthetic and real application workloads · 0.5
YearPublicationVenuePosition
2021 Dynamic application mapping on CTH network: a performance-centric approach
abstract
Communication cost in terms of energy consumption and network latency, along with the dynamic allocation time of the tasks and their execution time, is the primary design concern of a run-time mapping and scheduling strategy that may significantly affect the overall performance of an application. The present work proposes a dynamic mapping and scheduling algorithm based on the Cube-Tree-Hybrid (CTH) topology. The CTH network can integrate a large number of IP cores under significantly low network diameter, as opposed to mesh. Moreover, the design of CTH comes with considerable path diversity. For the above properties, mapping on CTH becomes simpler than mesh, which successfully minimizes the communication hop distance amongst various tasks of an application. Extensive experimentation has been done across several synthetic and real application workloads. Compared to the prevalent mesh-based mapping techniques, the proposed algorithm achieves a minimum gain of 56% on communication latency, whereas it is 36% in total power consumption. Minimum 14% improvement on applications' deadline satisfaction is achieved.
Avik Bose, Prasun Ghosal
SenSys1
2020 Switching at flit level: A Congestion Efficient Flow Control Strategy for Network-on-Chip
abstract
The proposed work demonstrates a novel flow control mechanism that brings the flexibility to route every flit of a packet independently, alleviating the network congestion more efficiently in Virtual Channel (VC) based NoC routing. A 100% buffer utilization is achieved by putting an end to the overhead of VC arbitration. The modified router design comes with a 20% area and 4.73% energy saving on the generic one. Packet Latency improvement of 35 -78 %, 27 - 68%, and 45 - 62% is observed over the mesh, torus, and flattened butterfly topologies respectively under uniform random traffic. The average packet drop rate is reduced by a minimum of 28% across the above topologies.
Avik Bose, Prasun Ghosal
PDP1
2020 A low latency energy efficient BFT based 3D NoC design with zone based routing strategy
Avik Bose, Prasun Ghosal
J. Syst. Archit.1