Demo Data from EDBT 2026 / reviewers in the wild / expert
A. J. Nichols
dblp:151/4708
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 1965
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 88% Integrated circuit design · 12% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 2 | 1965 | State Assignments in Combinational Networks · IEEE Trans. Electron. Comput. 1965 Minimal Shift-Register Realizations of Sequential Machines · IEEE Trans. Electron. Comput. 1965 |
Electronic design automation › logic synthesis
state assignment |
0.0 | 2 | 1965 | State Assignments in Combinational Networks · IEEE Trans. Electron. Comput. 1965 Minimal Shift-Register Realizations of Sequential Machines · IEEE Trans. Electron. Comput. 1965 |
Electronic design automation › logic synthesis
combinational logic synthesis |
0.0 | 1 | 1965 | State Assignments in Combinational Networks · IEEE Trans. Electron. Comput. 1965 |
Electronic design automation › logic synthesis › finite state machine synthesis
output encoding |
0.0 | 1 | 1965 | State Assignments in Combinational Networks · IEEE Trans. Electron. Comput. 1965 |
Integrated circuit design › digital circuit design
sequential circuit design |
0.0 | 1 | 1965 | Minimal Shift-Register Realizations of Sequential Machines · IEEE Trans. Electron. Comput. 1965 |
Electronic design automation › logic synthesis › sequential circuit synthesis
shift-register realization |
0.0 | 1 | 1965 | Minimal Shift-Register Realizations of Sequential Machines · IEEE Trans. Electron. Comput. 1965 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1965 | Minimal Shift-Register Realizations of Sequential MachinesabstractThis paper is concerned with the problem of mechanizing synchronous sequential machines with the least number of shift registers. An algorithm, suitable for programming on a digital computer, is developed which starts with the state table of the given machine and yields mechanizations having the least possible number of shift registers. The algorithm is based on the fact that there is a one-to-one correspondence between shift registers and certain partitions of the set of states of the machine. These partitions are called shift-register partitions (SRP's), and it is shown that every SRP can be generated from two special partitions called the column partition (πc) and the row partition (πr). States are grouped together in πcif they have transitions into common states and are grouped together in πrif they have transitions from common states. A. J. Nichols |
IEEE Trans. Electron. Comput. | 1 |
| 1965 | State Assignments in Combinational NetworksabstractThe problem of assigning codes to the output states of a multiple-output combinational circuit is considered. It is assumed that if the circuit has n inputs, then the 2nfundamental products, i.e., input states, are to be partitioned into disjoint groups, such that all members of the same group produce the same output state. The problem of coding the output states is studied here. Two algorithms for making the assignments are considered. The first gives those encodings for which the sum of the costs of all the output functions is minimum; the second minimizes the variable dependency of the output functions. In problems where reduced variable dependency is possible it has been found that the second algorithm yields minimum or near-minimum cost networks. Since this algorithm is easily applied it is useful for finding economical networks in situations where a large number of variables are involved since in such cases the first algorithm becomes lengthy. Attention is also directed to the problem of determining the optimum number of output variables to use for an encoding. An upper bound is derived and an example is presented which requires this bound. A. J. Nichols, A. J. Bernstein |
IEEE Trans. Electron. Comput. | 1 |
| 1963 | Comments on Armstrong's State Assignment Techniques
A. J. Nichols |
IEEE Trans. Electron. Comput. | 1 |