As embedded systems become integral in both academia and industry, hardware description languages are becoming a requisite part of Electrical and Computer Engineering curricula. The implementation of project-based learning in a freshman Digital Fundamentals course using an FPGA platform allows for greater engagement and learning through interesting and real-world projects. Through this approach, students strengthen the conceptual links between hardware description languages and circuit hardware while developing the ability to manage complex systems with multiple levels of abstraction. This paper discusses the implementation of three different application-driven projects on the Basys-3 trainer FPGA platform at the National University of Singapore and evaluates the effects of the key pedagogical differences. Both qualitative and quantitative assessment results are presented, showing how students perceived these projects and met the learning objectives.

The overall accuracy and linearity of a matching-limited successive-approximation-register analog-to-digital converter are primarily determined by its digital-to-analog converter's (DAC's) matching characteristics. As the resolution of the DAC increases, it is harder to achieve accurate capacitance ratios in the layout, which are affected by systematic and random mismatches. An ideal placement for the DAC array should try to minimize the systematic mismatches, followed by the random mismatch. This paper proposes a placement strategy, which incorporates a matrix-adjustment method for the DAC, and different placement techniques and weighting methods for the placements of active and dummy unit capacitors. The resulting placement addresses both systematic and random mismatches. We consider the following four systematic mismatches such as the first-order process gradients, the second-order lithographic errors, the proximity effects, the wiring complexity, and the asymmetrical fringing parasitics. The experimental results show that the placement strategy achieves smaller capacitance ratio mismatch and shorter computational runtime than those of existing works.