As 3-Dnandflash memory continues to scale toward higher density, significant reliability disparities arise among different pages in triple-level cell (TLC) flash, posing severe challenges to error-correction codes (ECCs) in the middle and late stages of flash lifetime. Polar codes have been introduced into flash storage systems due to their near-capacity performance; however, their decoding heavily relies on the accuracy of log-likelihood ratios (LLRs). Hard-decision sensing in flash memory leads to severe loss of soft information, thereby limiting the achievable error-correction performance. To address these challenges, this article proposes a page-aware reliability optimization scheme for polar codes in 3-D TLC flash memory. First, a page-aware polar bit mapping (PA-PBM) scheme is proposed, which exploits the mismatch between polar bit importance and page reliability by mapping critical bits to highly reliable pages and frozen bits to less reliable pages, thereby reducing the probability of critical errors. Building upon PA-PBM, a reliability-aware weighted polar mapping (RAW-PM) scheme is further developed, which incorporates page-level raw bit error rate (RBER) information to construct confidence-differentiated pseudo-soft LLRs and refines the bit mapping strategy, enabling weighted path metric (PM) correction and improving decoding accuracy under hard-decision sensing. Extensive experiments are conducted on a flash memory test platform to evaluate the proposed schemes. The results demonstrate that RAW-PM significantly improves the frame error-correction success rate in the middle and late stages of flash lifetime and reduces the post-ECC uncorrectable bit error rate (UBER) by more than one order of magnitude. Under typical large-scale access, RAW-PM introduces no additional read operations, requires no changes to the decoder architecture, and achieves these gains with minimal control and computational overhead, demonstrating excellent practical feasibility.

Three-dimensional (3-D)nandflash memory has emerged as the predominant solution for high-capacity nonvolatile data storage. However, the continuous increase in storage density has concurrently led to significant challenges in data reliability degradation. This article investigates the application of polar codes for error correction innandFlash memory. We propose a combined Monte Carlo (CMC) method to dynamically determine information bit positions in polar code encoding for flash memory chips under varying reliability statuses. For decoding, we identify that the hard-decision read mechanism in flash memory introduces extreme log-likelihood ratio (LLR) quantization effects. This quantization phenomenon may erroneously prune correct decoding paths during successive cancellation list (SCL) decoding, thereby degrading the error correction capability of polar codes. To address this critical issue, we develop a cascaded parity-check (PC)-assisted path pruning scheme integrated with the SCL algorithm. The experimental results demonstrate that the proposed polar code algorithm can significantly enhance the reliability of data storage innandflash memory. In the long code length scenario, the proposed polar decoding scheme with PC-assisted pruning achieves a maximum uncorrectable bit error rate (UBER) reduction of 98.62% compared to algorithms without PC. The proposed approach demonstrates an 8.56 times increase in the raw bit error rate (RBER) threshold for achieving 100% error correction success, significantly surpassing the performance of conventional low-density parity-check (LDPC) codes, especially toward the end of the flash memory’s lifespan.

As flash memory storage density continues to increase, it has become the mainstream storage medium for electronic devices. Writing data in low-temperature environment causes distortions in the flash memory threshold voltage distribution (TVD), which spikes the raw bit error rate and ultimately leads to degradation of the performance of flash-based electronic devices. To ameliorate the reliability problem caused by flash memory read and program temperature variations, this study proposes a flash memory programming temperature compensation algorithm based on read reference voltage (PTC-RRV) calibration. 3-D triple-level cell (TLC) flash memory is currently the mainstream storage medium for consumer electronics. Based on a large number of real tests on this type of chips, the relationship between the programming/reading temperature and the TVD of flash memory is fully characterized, and a programming temperature compensation model is constructed. The model evaluation results show that the PTC-RRV strategy can significantly reduce the average number of read-retry of low temperature written data and effectively improve the storage reliability and read performance of flash memory, whose optimization effect on electronic devices is better than the existing temperature compensation algorithms.

Low-density parity-check (LDPC) codes are now broadly employed as error correction code (ECC) solutions in NAND flash memories. With the rapid development of high-performance three-dimensional (3-D) NAND memories, mitigating the read latency caused by LDPC decoding attempts has emerged as an investigation focus. Existing investigations have demonstrated that efficient memory sensing is crucial to enhancing the efficiency of LDPC decoding attempts. The optimal memory sensing parameter options are determined by the threshold voltage distributions of NAND flash, which are difficult to be dynamically extracted during data retention. To address the issue, this article proposes an online lightweight strategy for threshold voltage distribution estimation, named LVDE. LVDE suggests a probe wordline design that uses one-read sampling to measure the threshold voltage distributions during long-term retention. Further, LVDE develops a methodology for the cross-layer estimation of threshold voltage distributions, thereby utilizing the measurements of the probe wordline to estimate those of each layer. LVDE is implemented on real flash chips to compare with numerous state-of-the-art strategies. Experimental results demonstrate that LVDE can significantly enhance the efficiency of LDPC decoding attempts and thus improve the read performance of 3-D NAND flash memory.

To enhance the reliability of 3-D TLC NAND flash memory, low-density parity-check (LDPC) codes have become widely adopted. However, as the number of read, program or erasures increases, the raw bit error rate (RBER) of read data in flash memory chips also rises, leading to the challenge of increased LDPC decoding latency. To address this, an idea of utilizing the decoding correct probability of LDPC to reduce latency is proposed. First, by analyzing the encoding method of TLC NAND flash memory, a single direction characterization error model based on the correlation between individual pages is constructed. Next, through experimental validation, the feasibility of using the number of iterations as an indicator of decoding correct probability is demonstrated, leading to the proposal of a low-overhead and high-performance Iterative Alternative Correct Probability Optimization (IACPO) scheme. Leveraging the fact that LDPC decoding exhibits a high success probability within a specific range of read data, the existence of successful decoding area (SDA) is confirmed through a large number of real experiments, and the distribution characteristics of SDA in TLC NAND flash memory are analyzed. Finally, the Utilizing LDPC Decoding Correct-Probability Optimization (ULDCO) scheme to further optimize latency is proposed. This scheme uses SDA to improve the probability of correct data reading, particularly in the middle and later stages of flash memory life, in combination with the IACPO scheme. Experimental results show that the proposed IACPO and ULDCO schemes are not only generally applicable but also achieve significantly iterative latency reduction by 73.43% and 81.51%, respectively, compared to traditional schemes, with negligible storage and computation overhead. These results clearly demonstrate the superior performance of the proposed schemes in reducing iteration latency.

Resistive random access memory (RRAM)-based in-memory computing (IMC) architectures are currently receiving widespread attention. Since this computing approach relies on the analog characteristics of the devices, the write variation of RRAM can affect the computational accuracy to varying degrees. Conventional write–verify (W&V) procedures are performed on all weight parameters, resulting in significant time overhead. To address this issue, we propose a training algorithm that can recover the offline IMC accuracy impacted by write variation with a lower cost of W&V overhead. We introduce a importance-driven weight allocation (IDWA) algorithm during the training process of the neural network. This algorithm constrains the values of less important weights to suppress the diffusion of variation interference on this part of the weights, thus reducing unnecessary accuracy degradation. Additionally, we employ a layer-wise optimization algorithm to identify important weights in the neural network for W&V operations. Extensive testing across various deep neural networks (DNNs) architectures and datasets demonstrates that our proposed selective W&V methodology consistently outperforms current state-of-the-art selective W&V techniques in both accuracy preservation and computational efficiency. At same accuracy levels, it delivers a speed improvement of$6\times \sim 32\times $compared to other advanced methods.

Low-density parity-check (LDPC) codes are widely employed in NAND flash memory to improve the reliability of data. However, LDPC has serious latency problems when the raw bit error rate (RBER) is high. The reason is that not only a sufficient sensing level is required to obtain accurate soft information, but also a high number of iterations are needed. To reduce the latency of LDPC, an Entropy-Based Double Nonuniform (EBDN) sensing algorithm is proposed in this paper. The basic idea of this algorithm is to exploit the entropy to quantify the nonuniformity of intra-state and inter-state. And the sensing levels are placed in a targeted manner based on the entropy, thereby significantly reducing the number of sensing levels without reducing the LDPC error correction performance. The experimental results show that the proposed algorithm can decrease the number of iterations of LDPC by approximately 70% and reduce the read latency by 34.52% compared with the traditional nonuniform sensing algorithm.

With the explosive growth of data storage demands, the storage density of flash memory continues to increase. However, the reliability and read performance of high-density flash memory are constantly declining. To address this issue, this study proposes a low-cost read reference voltage (RRV) calibration strategy based on random bit flips. In this study, the relationship between the random bit flips count (RFBC) of flash memory and the read reference voltage offset level (RRVOL) is characterized, and an RFBC-RRVOL conversion model is constructed. Subsequently, the characteristics of 3D flash memory RRV offset are thoroughly studied, and based on the observation results. A RRV grouping optimization scheme and RRV calibration range WL expansion scheme are proposed to achieve generalized calibration of all WLs in flash memory blocks. Experimental results indicate that the proposed strategy introduces a minimal storage overhead of only 15.26 KB, which reduces the raw bit error rate (RBER) of flash memory at the end of life (EOL) and increases the success rate of one time read to 99.89%. Such improvements greatly enhance the reliability of data storage and reading performance. These results demonstrate that the strategy has good practicality and effectiveness in addressing the reliability and read performance issues of high-density flash memory.

The low-density parity-check code (LDPC) has been widely used to significantly enhance the reliability of 3-D NAND flash memory. However, in cases where the raw bit error rate (RBER) of the data is high, it not only demands more sense levels but also requires a large number of iterations, leading to a notable read latency issue. To mitigate this challenge, this paper introduces an innovative lightweight latency decrease (LLD) scheme. Initially, by examining the correlation between the number of iterations and the hard decision level (HDL), a functional model that encapsulates the relationship between iteration and offset is established. Building upon this model, the all-wordlines latency decrease (AWLD) scheme is proposed. In an effort to further decrease latency, an in-depth analysis of the similarities among different wordlines within a flash memory block is conducted, leading to the development of an optimized one-wordline lightweight latency decrease (OWLLD) scheme. For scenarios involving random reading of small data volumes, the interplay between function models of various overlapping regions is delved into, which ultimately results in the proposal of a further optimized one-page lightweight latency decrease (OPLLD) scheme. Experimental findings reveal that the OPLLD scheme can enhance the iterative performance of LDPC by up to 94.63% and reduce latency by up to 66.89% compared to traditional algorithms, while incurring minimal storage and computational overhead. This clearly indicates that the proposed scheme substantially enhances the read latency performance of LDPC in flash memory.

The 3-D flash memory is gradually becoming the mainstream nonvolatile storage medium due to its high capacity and high performance. However, interlayer interference during 3-D flash programming leads to significant differences in the error characteristics of edge and inner word lines; interlayer interference becomes more pronounced as the number of stacked layers increases, seriously affecting data storage reliability. In this study, many actual tests were conducted on triple-level cell (TLC) and quad-level cell (QLC) flash memory, which are the mainstream storage media in the current consumer market, to obtain the edge and inner word-line threshold voltage data under the interference of different factors, such as retention loss and read disturb; then, the threshold voltage difference between the edge and inner word lines under different conditions was quantitatively analyzed. An edge word-line reliability optimization strategy is proposed based on the read-reference voltage extra offset (RRVEO). Experimental results show that this strategy can reduce the edge word-line raw bit error rate (RBER) by more than 90% and eliminate the reliability difference between inner and edge word lines without significant overhead, thus significantly improving the data storage reliability of flash memory.

With the increasing density of flash memory, its service life is declining. As the most important technical index of a flash device, flash retention parameters often need to consume a substantial amount of time to be tested. With a view toward reducing the test period, the most popular method currently is to speedup the retention loss of flash memory at high temperatures. However, since the retention loss of flash memory is the result of a mixture of multiple failure mechanisms, the Arrhenius model with a single apparent activation energy ($E_{aa}$) has significant limitations in calculating the high-temperature acceleration factor for the retention loss of flash memory. In this article, based on a large number of real experiments, we have studied the retention characteristics of the flash memory in high-temperature environments and closely tracked the change of$E_{aa}$at different temperatures, retention time, and program/erase (P/E) cycle count. The experimental results show that the equivalent acceleration factor (AF) grows rapidly with retention time at the beginning of flash retention and that flash with a high P/E cycle count has a faster AF growth rate.

With the wide application of NAND flash storage systems in read-intensive memory, the corresponding reliability enhancement strategies for mitigating read disturb become the focus of investigations in recent years. The prior investigations have reported the strategies based on data modulation and verified their effectiveness in mitigating retention loss. The most significant advantage of these strategies is that they can often achieve significant reliability enhancement effect with great read performance, since they are usually based on asymmetric coding. This feature means that they have the potential to be ideal reliability enhancement strategies for read-intensive memory applications. To propose a universal and highly reliable data storage strategy, this article first observes the error modes at the cell-state level under the reliability stresses of retention loss and read disturb with floating-gate (FG) 3-D triple-level (TLC) NAND flash, and then proposes a target cell states elimination (TCSE) coding strategy for further restraining bit errors. In addition, this article for the first time reports the extra bit errors generated in the decoding process of the storage strategies based on data modulation, and defines the concept of transfer factor (TF) for evaluation. By using the proposed TCSE, the experimental results show that the overall bit error rate (BER) can be reduced by 80%–90% on average, compared with the raw random data pattern.

According to the appearance frequency of nibble short code, this paper presents a novel nibble remapping coding (NRC) strategy to increase the ratio of “1”s in the programming data of NAND flash memory. Because the NRC strategy does not change the length of data during encoding and decoding process, it does not consume any extra user data area of NAND flash. In addition, it can be transparently fit within the flash translation layer algorithms. The experimental results show that the NRC strategy reduces the program disturb errors by 56.9% and decreases the data retention errors by 52.5%, while experiencing only 2.2% degradation in writing speed and 3.2% degradation in reading speed. Compared with conventional BCH code, NRC can significantly enhance the efficacy of the out-of-band space to improve the storage reliability.

With aggressive scaling and multilevel cell technology, the reliability of NAND flash continuously degrades. The lifetime of NAND flash is highly restricted by the bit error rate (BER), and error-correcting codes (ECCs) can provide only limited error correction capability to tolerate increasing bit errors. To cope with this issue, a novel page endurance variance aware (PEVA) strategy is proposed to extend the lifetime of NAND flash based on the experimental observations from our hardware-software codesigned experimental platform. The experimental observations indicate that the BER distribution of retention error shows distinct variances in different pages. The key purpose of PEVA is to exploit the lifetime potency of every page in a block by introducing fine-grained bad page management instead of coarse-grained bad block management (BBM). The experimental results show that the PEVA can extend the lifetime of 2×-nm NAND flash by 9.8× compared with the conventional BBM and that there is at most an 8.7% degradation in writing speed compared with the traditional sector mapping technology. In addition, the maximum writing response time increased by at most 5.9% during the operation of the PEVA strategy.

The lifetime of NAND flash is highly restricted by the bit error rate (BER), while error-correcting codes (ECC) can provide only limited error correction capability to tolerate increasing bit errors. In this paper, a novel fixation ratio of error locations aware (FRELA) strategy is proposed to prolong the reliable retention time of flash memory. The concept of FRELA is motivated by following two observations obtained from our real hardware experimental platform: first, the increasing trend of average BER with the retention time and the program/erase cycles can be easily modeled; second, there is a great possibility that an error bit of flash memory remains wrong after a certain retention time. The key purpose of FRELA is to flip the corresponding data bits according to the locations recording of error bits prior to operating ECC. By virtue of the BER prediction model, the required storage space of FRELA is effectively reduced because it avoids updating the information of locations frequently. The experimental results show that FRELA can prolong the reliable retention time of 2×-nm NAND flash by more than 60% without stronger ECC, while experiencing at most 1.03% degradation in writing speed and 0.79% degradation in reading speed, respectively.

In this paper we describe a hardware-software co-design experiments platform for NAND flash based on Zynq. Our novel experimental platform utilizes the PL (Programmable Logic within Zynq) to achieve the timing control and bad block management of NAND flash, and to provide a high-speed parallel algorithm verification environment for users. Besides, it utilizes the PS (Processing System within the Zynq) to achieve the famous hybrid FAST FTL algorithm, so it can also provide a valuation baseline of FTL algorithms, and provide the running environment for compute-intensive data processing algorithms, like compression or error correction. Test results show that our experiment platform has a high speed and stable performance to manage the storage data, and can effectively evaluate the indicators of storage system based on NAND flash.