Accurate and efficient prerouting timing estimation is particularly crucial during placement to alleviate time-consuming design iterations. Machine-learning (ML)-based methods have been introduced recently to predict the post-routing timing results at placement stage, but most of them neglect the impact of timing optimization during physical design, suffering from accuracy loss due to inconsistent circuit netlist. In this work, an optimization-aware prerouting timing prediction framework based on multimodal learning is proposed to calibrate the timing changes between placement and routing stages, where the local netlist and layout information are extracted by graph neural network (GNN) and convolutional neural network (CNN), respectively, while the global information along the path is further extracted by Transformer network. Based on the predicted post-routing timing results by the proposed framework, timing optimization guidance is generated to enhance traditional design flow with better physical implementation quality. Experimental results demonstrate that for the OpenCores benchmark circuits under TSMC 22nm process, the proposed framework achieves significant correlation and accuracy improvement with an average of 0.9219 in terms of R2 score and 2.12% of mean absolute percentage error (MAPE) as well as an average runtime acceleration of$645\times $compared with traditional design flow on testing designs. With the timing optimization guidance, significant worst negative slack (WNS) and total negative slack (TNS) improvement are achieved compared with traditional flow after placement and routing, respectively, without noticeable area, power, wire length, and the number of design rule check (DRC) violations increase.

Statistical timing characterization for standard cell library poses significant challenge to accuracy and runtime cost. Prior analytical and machine learning-based methods neglect the profound influence induced by layout-dependent parasitic resistor and capacitor (RC) network in cell netlist as well as the timing correlation between topological structures of cells and process, voltage, and temperature (PVT) corners, resulting in tremendous simulation effort and/or poor accuracy. In this work, an accurate and efficient statistical cell timing library characterization framework is proposed based on heterogeneous graph attention network (HGAT) assisted with parasitic RC reduction approach, where the transistors and parasitic RC in cell are represented as heterogeneous nodes for graph learning and redundant RC nodes are removed to alleviate node imbalance issue and improve prediction accuracy. The proposed framework was validated with TSMC 22nm standard cells under multiple PVT corners to predict the standard deviation of cell delay with the error of 2.67% on average for all validated cells in terms of relative Root Mean Squared Error (rRMSE) with $3 \times $ characterization runtime speedup, achieving $2.7 \sim 6.9 \times $ accuracy improvement compared with prior works. The predicted statistical timing libraries were further validated with ISCAS’89 benchmark circuits for statistical static timing analysis (SSTA), where the critical path delay at $3 \sigma$ percentile point is reported with the average mismatch of $1.34 ps$ compared with foundry-provided library, showing $10.7 \sim 14.5 \times $ better accuracy than the competitive approaches.

Accurate and efficient pre-routing timing estimation is particularly crucial in timing-driven placement, as design iterations caused by timing divergence are time-consuming. However, existing machine learning prediction models overlook the impact of timing optimization techniques during routing stage, such as adjusting gate sizes or swapping threshold voltage types to fix routing-induced timing violations. In this work, an optimization-aware pre-routing timing prediction framework based on heterogeneous graph learning is proposed to calibrate the timing changes introduced by wire parasitic and optimization techniques. The path embedding generated by the proposed framework fuses learned local information from graph neural network and global information from transformer network to perform accurate endpoint arrival time prediction. Experimental results demonstrate that the proposed framework achieves an average accuracy improvement of 0.10 in terms of R2score on testing designs and brings average runtime acceleration of three orders of magnitude compared with the design flow.

Timing-driven placement is crucial in physical design flow with significant impact on later routability and ultimate manufacturability, which may deviate from finding the optimal solution and/or lead to unnecessary iterations, suffering from interleaved optimization steps and the corresponding inaccurate timing estimation. To solve this issue, we propose a Physical and Timing Aware framework with Graph Neural Network, PTA-GNN, which provides the candidate gate sizing and buffer insertion solutions as well as the timing constraint for potential violated paths as guidance to improve placement quality significantly. Experimental results on the OpenCores benchmarks with 22nm technology demonstrate that the proposed placement optimization framework achieves up to 89.09% worst negative slack (WNS), 55.47% total negative slack (TNS) improvement and 25.36% reduction on the number of violating paths (#VP). Our framework benefits the later routing stage with 2.19% wire-length decrease and 22% runtime reduction compared to standard physical design flow.

Gate sizing is an NP-hard problem to achieve Performance, Power and Area (PPA) optimization. Recently proposed learning-based approaches struggle to overcome the runtime issue of traditional heuristics, but lack the consideration of the intrinsic features for candidate gates in library and could not address the inequality issue of candidate sizes for different gates properly, suffering from insufficient design space exploration and inaccurate sizing assignment. In this work, based on a variant of generative adversarial network, Leak Adversarial Generation (LAG), a novel LAG-Sizer is proposed to model gate sizing as sequence generation problem, which breaks the traditional adversarial network by leaking the discriminator feature information into the generator to guide sizing generation. Feature fusion technique is introduced to comprehensively consider circuit feature and cell library feature while a unified classification is proposed to perfectly solve the inequality issue for sizing. The proposed sizer was validated with IWLS2005 and Opencores benchmark circuits under 22nm process. Experimental results demonstrate that an average of 4.6% Total Negative Slack (TNS) improvement and 15.6% number of violating endpoints (NVE) reduction are achieved by this work with similar area and power consumption compared to commercial tools as well as significant runtime speedup of 47.8×.

Timing mismatch between different stages of physical design poses great challenges for circuit optimization to achieve the desired performance, power, and area (PPA) tradeoff. The inaccurate timing estimation prior to routing may lead to over-design with unwanted power and area consumption or iterating back to cell placement at the cost of design turn-around time. Existing learning models could not predict post-routing circuit timing with satisfying accuracy and efficiency due to the limitations of the ignorance of delay correlation along the timing path and the empirical feature selection solutions. In this work, an accurate and efficient prerouting path delay prediction framework is proposed by utilizing a transformer network and residual model with an ensemble feature selection mechanism. Owing to the combined filter and wrapper methods, an ensemble feature selection mechanism is implemented to determine the optimal feature subset based on the timing and physical information at the placement stage for path delay prediction, which is extracted as feature sequences for each cell along the timing path to be trained by transformer network. With the residual model, the predicted timing mismatch between the placement and routing stages by the transformer network is further calibrated to estimate the post-routing path delay. The proposed framework has been validated with ISCAS’85 and OpenCores benchmark circuits for the prediction of post-routing path delay, where the perdition error in terms of relative root mean squared error is limited within 1.3% and 3.0% and the correlation coefficient$R$is higher than 0.999 and 0.995 for seen and unseen circuits, respectively, indicating an error reduction by 2.3–10.6 times compared by prior learning-based models. In addition, the framework achieves average three orders of magnitude speedup compared with the commercial tools and is accelerated by a factor of 14–128 as against the competitive learning models, which is promising to be applied to guide design optimization prior to time-consuming routing stage.

Engineering change order (ECO) plays an important role in design flow to perform leakage optimization with gate-sizing and$V_{\mathrm{ th}}$assignment approaches. Unfortunately, it is extremely time consuming due to the iterative nature of cell swap and timing check. Many learning-based methods, especially, graph neural networks (GNNs), have been utilized in leakage optimization to predict$V_{\mathrm{ th}}$assignment, but most of them treat the cells and their neighborhood cells uniformly when aggregating cell-level topology information to gather design-level information and discard the path-level information, suffering from accuracy loss, which could be exploited by bidirectional long short-term memory (BiLSTM) network. In this work, a GNN-BiLSTM-based framework is proposed to perform commercial-quality$V_{\mathrm{ th}}$assignment for leakage optimization by learning design-level and path-level information and is validated with the benchmarks from Opencores and IWLS 2005 under TSMC 28 nm technology. The experimental results demonstrate that the proposed framework achieves the most accurate$V_{\mathrm{ th}}$assignment prediction compared with the competitive models with F1-score ranging from 0.954 to 0.975 for seen designs and from 0.945 to 0.965 for unseen designs, respectively. The divergence between the leakage optimization results of this work and the commercial tool is limited to be between 8.5% and 26.1%, which is reduced by at least$2.2\times $compared with prior works. Owing to efficient training convergence and inference speed, our approach achieves significant runtime improvement by up to$10\times $over commercial tool with similar leakage optimization results.

Timing estimation prior to routing is of vital importance for optimization at placement stage and timing closure. Existing wire- or net-oriented learning-based methods limits the accuracy and efficiency of prediction due to the neglect of the delay correlation along path and computational complexity for delay accumulation. In this paper, an efficient and accurate pre-routing path delay prediction framework is proposed by employing transformer network and residual model, where the timing and physical information at placement stage is extracted as sequence features while the residual of path delay is modeled to calibrate the mismatch between the pre- and post-routing path delay. Experimental results demonstrate that with the proposed framework, the prediction error of post-routing path delay is less than 1.68% and 3.12% for seen and unseen circuits in terms of rRMSE, which is reduced by 2.3~5.0 times compared with exiting learning-based method for pre-routing prediction. Moreover, this framework produces at least three orders of magnitude speedup compared with the traditional design flow, which is promising to guide circuit optimization with satisfying prediction accuracy prior to time-consuming routing and timing analysis.

Dispatching and control information freshness conducts an important impact on the training accuracy of distributed energy dispatching and control model. Poor information freshness will increase the loss function of the training model, and reduce the reliability and economy of dispatching and control. Simplified power internet of things can provide plug-and-play and multi- mode fusion communication support, but it still faces challenges of the coupling of model training and data transmission as well as the difficulty in guaranteeing dispatching and control information freshness. In this paper, a semi-distributed federated learning- based framework for dispatching and control model training decision-making is proposed, and a dispatChing and control informAtion fReshness-aware batch size Optimization aLgorithm (CAROL) is presented. CAROL leverages deep Q network and dispatching and control information freshness awareness to learn the batch size optimization strategy. CAROL can minimize model loss function while guaranteeing long-term dispatching and control information freshness constraints. Compared with existing feder- ated learning algorithms, CAROL achieves superior performance in global loss function and information freshness.

The reliable operation of doubly-fed induction generator (DFIG) wind turbine (WT) systems rely on the accurate information of states. However, due to the unavailability of some states from phasor measurement units (PMUs), dynamic state estimation (DSE) for DFIG-WT connecting to the power system becomes essential. Although various DSEs have been applied, the variable stochastic wind speed was excluded into consideration, leading to the inaccurate estimation results. This paper develops the DSE using centralized Kalman filter (CKF) for DFIG-WT under the stochastic wind speed. The wind speed is modeled by stochastic differential equations (SDE), which can generate the trajectories with statistical properties similar to the wind speed historical data available for a particular location, so that the variable wind speed can be applied to the filtering process. Finally, the system involving a DFIG connected to a standard IEEE 14-bus system is utilized to verify the feasibility of the proposed method with the occurrence of electric faults.

Non-inverting Buck Boost converters (NIBB) have been utilized as interfacing converters for energy storage, due to the high steady-state efficiency offered by the asynchronous control. However, classical asynchronous control has inherent poor dynamic performance when the input and output voltages are near. To solve the problem, concept of “dynamic mode switching” is first proposed in this paper. Instead of limiting operation of NIBB to buck mode during voltage step-down conversion, and to boost mode during voltage step-up conversion, switching state is selected flexibly. Performance of proposed control strategy is compared with “the performance limit of asynchronous control” and “classical PI control”. The proposed dynamic mode switching shows improved voltage deviation and recovery time.