The presence of faults in distributed executions can compromise the production of results without proper fault management techniques. The current de-facto standard for inter-process communication, MPI, lacks these features, precluding its effectiveness at a massive scale. Previous efforts produced all-in-one frameworks for fault management, but most of these works leverage checkpoint and restart functionalities, impacting the performance and scalability of the executions. Unlike those, the Legio framework adopts a graceful degradation solution, sac-rificing result accuracy for faster recovery and lower overhead. Still, it cannot handle all the faults: there may be some critical processes whose failure irremediably compromises the result of the computation. With this work, we extend the Legio framework to support critical process faults, combining the benefits of checkpoint and restart solutions with a graceful degradation approach. The experimental campaign shows that our extension does not introduce significant overheads in the executions while correctly managing the failure of critical processes.

Abstract The Software Heritage (SWH) dataset represents an invaluable source of open-source code as it aims to collect, preserve, and share all publicly available software in source code form ever produced by humankind. Although designed to archive deduplicated small files thanks to the use of a Merkle tree as the underlying data structure, querying the SWH dataset presents challenges due to the nature of these structures, which organize content based on hash values rather than any locality principle. The magnitude of the repository, coupled with the resource-intensive nature of the download process, highlights the need for specialized infrastructure and computational resources to effectively handle and study the extensive dataset housed within SWH. Currently, there is a lack of infrastructures specifically tailored for running analytics on the SWH dataset, leaving users to handle these issues manually. To address these challenges, we implemented the SWH-Analytics (SWHA) framework, a development environment that transparently runs custom analytic applications on publicly available software data preserved over time by SWH. Specifically, this work shows how SWHA can be effectively exploited to study usage patterns of free and open-source software licenses, highlighting the need to improve license literacy among developers.

Today digital revolution is having a dramatic impact on the pharmaceutical industry and the entire healthcare system. The implementation of machine learning, extreme-scale computer simulations, and big data analytics in the drug design and development process offers an excellent opportunity to lower the risk of investment and reduce the time to the patient.

MPI version 4.0 introduces new functionalities like the Session model but still lacks fault management mechanisms. Past efforts produced tools and MPI standard extensions to manage fault presence, including User Level Fault Mitigation (ULFM). These measures are effective against faults but do not fully support the new additions to the standard. In this paper, we combine the fault management possibilities of ULFM with the new Session model functionality introduced in version 4.0 of the standard. We focus on the communicator creation procedure, highlighting criticalities and proposing a method to circumvent them. The experimental campaign shows that the proposed solution does not significantly affect execution times and scalability while better managing the arise of faults.

The new open and royalty-free RISC-V ISA is attracting interest across the whole computing continuum, from microcontrollers to supercomputers. High-performance RISC-V processors and accelerators have been announced, but RISC-V-based HPC systems will need a holistic co-design effort, spanning memory, storage hierarchy interconnects and full software stack. In this paper, we describe Monte Cimone, a fully-operational multi-blade computer prototype and hardware-software test-bed based on U740, a double precision capable multi-core, 64 bit RISC-V SoC. Monte Cimone does not aim to achieve strong floating point performance, but it was built with the purpose of "priming the pipe" and exploring the challenges of integrating a multi-node RISC-V cluster capable of providing an HPC production stack including interconnect, storage and power monitoring infrastructure on RISC-V hardware. We present the results of our hardware/software integration effort, which demonstrate a remarkable level of software and hardware readiness and maturity - showing that the first-generation of RISC-V HPC machines may not be so far in the future.

On the race toward exascale supercomputing systems are facing important challenges which limit the efficiency of the system. Among all, power and energy consumption fueled by the end of Dennard's scaling start to show their impact on limiting supercomputers peak performance and cost effectiveness.