EDBT 2026 Demo / reviewers in the wild / expert
Byul Hur
dblp:152/4041
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Energy-efficient computing · 91% Interconnection networks and networks-on-chip · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Energy-efficient computing
leakage power reduction |
0.5 | 1 | 2021 | A Voting Approach for Adaptive Network-on-Chip Power-Gating · IEEE Trans. Computers 2021 |
Energy-efficient computing
power gating |
0.5 | 1 | 2021 | A Voting Approach for Adaptive Network-on-Chip Power-Gating · IEEE Trans. Computers 2021 |
Energy-efficient computing
power management |
0.5 | 1 | 2021 | A Voting Approach for Adaptive Network-on-Chip Power-Gating · IEEE Trans. Computers 2021 |
Interconnection networks and networks-on-chip › routing algorithms
adaptive routing |
0.1 | 1 | 2021 | A Voting Approach for Adaptive Network-on-Chip Power-Gating · IEEE Trans. Computers 2021 |
Methods — techniques the papers use, named apart from their topics
voting-based power-gating policy · 0.5synthetic and real workload evaluation · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | A Voting Approach for Adaptive Network-on-Chip Power-GatingabstractScalable Networks-on-Chip (NoCs) have become the standard interconnection mechanisms in large-scale multicore architectures. These NoCs consume a large fraction of the on-chip power budget, where the static portion is becoming dominant as technology scales down to sub-10nm node. Therefore, it is essential to reduce static power so as to achieve power- and energy-efficient computing. Power-Gating as an effective static power saving technique can be used to power off inactive routers for static power saving. However, packet deliveries in irregular power-gated networks suffer from detour or waiting time overhead to either route around or wake up power-gated routers. In this article, we proposeFly-Over (Flov), a voting approach for dynamic router power-gating in a light-weight and distributed manner, which includesFlovrouter microarchitecture, adaptive power-gating policy, and low-latency dynamic routing algorithms. We evaluateFlovusing synthetic workloads as well as real workloads from PARSEC 2.1 benchmark suite. Our full-system evaluations show thatFlovreduces the power consumption of NoC by 31 and 20 percent, respectively, on average across several benchmarks, compared to the baseline and the state-of-the-art while maintaining the similar performance. Jiayi Huang 0001, Shilpa Bhosekar, Rahul Boyapati, Byul Hur, Ki Hwan Yum, Eun Jung Kim 0001 |
IEEE Trans. Computers | 5 |