With the end of Moore’s law and Dennard scaling, waferscale systems or processors that integrate multiple pre-tested known good dies (KGDs) on a waferscale-interposer are new approaches to further improve the chiplet-based system’s performance. This article explores the network on wafer (NoW) architecture of waferscale switching system under several physical constraints. A software-based approach is proposed to redefine the topological property. A five-level butterfly fat-tree (BFT)-like logical topology with 8.96-Tb/s (896 ports$\times 10$Gb/s/port) switching bandwidth is achieved based on 2-D-mesh-like physical topology. We show that the proposed BFT-like topology with breadth-first-search (BFS) based traffic balanced routing algorithm reduces 55.6% hops, 41.4% transmission delay, and improves 24.2% throughput compared to 2-D-mesh-like topology under different traffic distributions. This BFT-like waferscale switching system is suitable for high-performance computing and data centers. In addition, the numerical analysis shows that the waferscale package can provide significant power efficiency and latency advantages compared to the typical single-chip package, which mainly benefits from the short-reach IO requirements. Note that the proposed waferscale switching system is compatible with high-switch-capacity dies with advanced process technology, which can further improve system performance. Finally, we present the physical implementations for the waferscale system with heterogeneous dies.

With the end of Moore's Law and Dennard scaling, waferscale systems that integrate multiple pre-tested known good dies (KGDs) on a waferscale-interposer are new approaches to further improve chiplets-based systems' performance. This paper explores the manufacturing defects of waferscale systems and the effect to network on wafer (NoW). A traffic-balanced routing algorithm is proposed for the irregular network with multiple faults of NoW. The results show that the routing algorithm reduces transmission delay by 57% and improves throughput by 36.4% compared to the normal breadth-first-search algorithm. Besides, we build a throughput model by using the nonlinear least squares method (NLLS) with the parameters of faults number, location and concentration ratio. The results show that the model can reach 0.98 goodness of fit and accurately predict the throughput performance of different irregular NoW topologies. The model can be used to predict the system performance and avoid critical faults of the physical waferscale switching system.