As the technology scaling has happened, logic performance has improved at a much faster rate than SRAM performance. Therefore, in SRAMs, required performance improvement is achieved by design and architecture level changes. This work presents pipelined hierarchical SRAM and compares it with a conventional non-hierarchical SRAM design on the axes of Performance, Power, and Area. We show that a pipelined SRAM of size 8192×64 m16 with integrated burst mode, operates at 40% lesser dynamic power and is 31% faster than a conventional non-hierarchical SRAM design in 65nm Low stand-by Power(LSTP) CMOS technology. When compared to hierarchical design, it operates at 19% lesser dynamic power and is 17% faster with an area increase of 5%.

Framework is developed for estimation of power at pre register transfer level (RTL) stage for structured memory sub-systems. Power estimation model is proposed specifically targeting power consumed by clock network and interconnect. The model is validated with VCD-based simulation on back-annotated netlist of an 8 MB memory sub-system used as video RAM (VRAM) for high-end graphics applications. This methodology also forms the basis for low-power exploration driving floor plan choice, gating structure of data, and clock network. We demonstrate 57% reduction in dynamic power by using low-power techniques for the 8 MB VRAM used as frame buffer in a graphics processor. FALPEM can be extended to other applications like processor cache and ASIC designs.

We propose adaptive negative bit line write assist (WA) circuit for static random access memory (SRAM). It provides controlled overdrive voltage (or negative bump) across the full range of operating voltage. This allows dynamic voltage and frequency scaling without penalizing the reliability at higher voltage and temperature. Design is implemented in CMOS 32NM low power technology for dual port (DP) SRAM bit cell 0.390u2 (DP390) having a normal operating range from 0.9 to 1.1 V, extended to 0.75-1.1 V by utilizing proposed WA circuit. This design has an area overhead of 4.5%. Write cycle performance improvement and dynamic power reduction achieved is 10% and 8%, respectively, at 0.9 V with respect to the design without WA.