NIST selected ASCON as the standard Lightweight Cryptography (LWC) algorithm in 2023. ASCON’s implementations promise bringing lightweight Authenticated Encryption (AEAD) to resource-constrained devices surpassing Advanced Encryption Standard (AES) implementations. In this work, a standard compliant ASCON Application Specific Integrated Circuit (ASIC) hardware (HW) is designed and fabricated using CMOS GF22FDx technology. This study provides a quantitative assessment of the HW with two other standard compliant implementations of ASCON. One is software implementation (SW), and the other is a hardware accelerated (HW/SW co-design) implementation. The assessment shows that HW outperforms the SW implementation by up to three orders of magnitude in energy efficiency and throughput, whereas HW/SW co-design throughput and energy efficiency falls in the middle between HW and software. ASCON ASIC HW is also compared with a standard HW implementation of the AES fabricated over the same chip. ASCON uses only 39% of AES’s area and boosts energy efficiency by up to 25 times. To the best of our knowledge, this work is the first work providing a silicon-based analysis for ASCON ASIC implementation reaching a throughput of 4.3 Gbps @ 0.8V and 2 Gbps @ 0.6V, and energy efficiency of 1.9 Tb/J @ 0.8V and 3.5 Tb/J @ 0.6V in$2505~\mu $m2 on GF22FDx at 620MHz @ 0.8V. Furthermore, the comparative assessments between different implementations of ASCON guides the implementation choice for specific deployments to meet the demands of secure processing in dust-size sensors, edge and IoT.

Current cryptographic algorithms are designed for server environments prioritizing security with no limitations on hardware resources. They may not be suitable for emerging resource-constrained devices used in areas such as Edge computing, UAV, and IoT. For such constrained devices, many LWC algorithms have been proposed, however, there is no FIPS standard yet. So, NIST initiated a standardization process for a LWC FIPS standard. Finalists are announced with 10 algorithms after two rounds of evaluation. The aim of this work is to design and evaluate the hardware of these candidates using ASIC synthesis over GF 22nm CMOS technology. The evaluation focuses on energy efficiency using bit/joule as the main metric. Other metrics such as throughput and area are evaluated as well. Results show a great discrepancy in the energy efficiency between the finalists. For example, TinyJambu, Xoodyak and ASCON achieved 10-25 times better energy efficiency compared to ISAP, Elephant, and Grain-128AEAD while processing the same number of bits.

Parallelism and pipelining are widely used to improve the performance and throughput of systems. However, its effect on energy consumption needs to be studied. In this paper the alteration in energy consumption that results from using parallel architecture is studied over LWC algorithms from NIST standardization process. Ten algorithms are currently in the final round of the standardization process. Two algorithms out of the ten final round candidates can be parallelized which are Elephant and ISAP algorithms. For these algorithms, both iterative looping and parallel architectures are designed and synthesized over ASIC GF22nm technology. Then both architectures are compared in terms of area, throughput and energy. Results showed an enhancement in energy efficiency up to 49% and 28% and throughput improvement reaches up to 96% and 45% in Elephant and ISAP, respectively.