Memory BIST implements March test techniques extensively for testing embedded memories on a chip. A high-complexity test algorithm like the March MSS (18N) can guarantee the detection of all unlinked static faults in SRAM. In contrast, March algorithms with lower complexity can be used to reduce test costs and chip area overhead. Still, they have poor coverage of faults identified in the nanometer process technologies. Subsequently, a balance between the fault coverage (FC) and the test cost is necessary. This article presents a method to generate new March algorithms that provide optimum coverage on faults introduced by the nanometer process technologies. It was achieved by developing automated software to generate the new Data Background sequence and rearrange the existing March algorithms’ test operations to remove redundancies and enable the sensitization and detection of the intended faults while preserving their complexities. Comprehensive fault detection analyses were conducted to assess their FCs and to find any removable redundant test operations. The proposed method produced new March AZ1 and March AZ2 algorithms, with 13N and 14N complexity, respectively, that provide optimum coverage of the targeted faults. They were successfully implemented in the Memory BIST controllers, and their functionalities were validated via simulations.