This article presents a chopperless ripple-free low-noise bandgap reference (BGR) circuit in a traditional CMOS process that uses only p-n-p bipolars. Almost all chopperless bandgap structures require the use of n-p-n bipolars in special twin well processes, and they are prone to substrate and power supply noise. This work has targeted the “chopperless” scenario in p-n-p bipolar-based bandgap architecture by presenting a low offset temperature coefficient (TC) preamplifier design in the error amplifier. Notably, the design’s worst case power supply rejection (PSR) was “derived, simulated, and experimentally measured” to be −35 dB at 7.5 MHz, which is above par with any previously designed circuits. Furthermore, for the first time, an extensive mathematical analysis is provided for the self-bias loop, which is traditionally used to suppress the systematic offset. The prototype implemented in the TSMC 65-nm low-power (LP) process is untrimmed and occupies an active area of 0.0226 mm2 while drawing a current of$48.36~\mu $A from 0.9-V supply. Measurement results of 28 chips and 10 chips in two different wafers show that the achieved nominal reference voltage of 500 mV has an average accuracy of 27 ppm/°C, similar to the curvature uncompensated BGR that uses chopping. Furthermore, the measured noise spectral density at 1-Hz offset is$10~\mu $V/$\sqrt {(}\text {Hz})$, which is the state of the art among chopperless bandgap structures.

A curvature-compensated bandgap voltage reference circuit that generates 1.317 V from a 1.8V supply is presented in this paper. The PTAT voltage generated in the proposed architecture is the sum of the difference in the gate-source voltage of weakly inverted MOS transistors and the difference in the emitter-base voltages of bipolar. This results in inherently higher PTAT voltage generation. Furthermore, this architecture significantly eases the opamp's requirements on offset and flicker noise and doesn’t require sophisticated techniques, such as chopping. A novel curvature compensation scheme is proposed and validated across PVT simulations and achieves 7 ppm/°C with a single point trim. The proposed bandgap consumes a current of 90 μA from 1.8V supply and occupies an area of 0.0125 mm2in TSMC 65nm.

This paper presents a fixed transconductance circuit based on the impedance matching. The proposed technique does not depend on the square law model of the transistors and tracks the resistor for all operating regions of the transistor. Unlike its predecessors, the transconductance of the transistor tracks for a wide range of external resistors. Such techniques find applications in analog and mixed-signal circuits like data converters, voltage- controlled oscillators, amplifiers, etc. The proposed circuit is implemented in the TSMC 65nm LP process, and it occupies an area of 55μm x 24μm. The transconductance varies about 0.8% over a nominal value of 125μS across process corners and temperature. Monte Carlo simulation results show a standard deviation of 4.64 μS over a mean of 125.8 μS.

This paper reports the measurements of thermo-mechanical package stress effects on High Resistivity Polysilicon Resistors (HRI-poly) and presents guidelines for the optimal placement of such resistors to minimize variations due to stress. The chip center is considered the radial axis, and nine HRI resistors are placed at different radii and angles from it. The test structures are fabricated in a 180nm CMOS process. Thermo-mechanical package stress affects the value of resistors depending on their location. It is observed that the resistors placed close to the chip center and aligned perpendicular to the radial line have the least effective mismatch due to stress/temperature. The resistors placed close to the chip edge, and parallel to the radial line have the maximum effective mismatch due to temperature/stress. The paper presents the analysis along with the guidelines for placing the resistors.

In this paper, a curvature-compensated bandgap reference circuit is presented which generates 0.538V from 0.85V supply voltage. The PTAT voltage generated in the bandgap core is added to the partial CTAT voltage to generate the sub-bandgap reference, reducing the CTAT current mirror mismatch. Furthermore, this architecture eases the opamp's requirements on offset and flicker noise significantly and doesn't require sophisticated techniques, such as chopping. A novel curvature compensation scheme is proposed and validated across PVT simulations and achieves 12 ppm/°C with a single point trim. The proposed bandgap consumes a power of 15 μW and occupies an area of 7315 μm2in TSMC 28nm.