In high-illumination environments, conventional object detection systems suffer from severe performance degradation due to pixel saturation, which leads to information loss in overexposed regions. To address this issue, we propose a WDR (wide dynamic range) binary image fusion and detection system, which enhances object visibility and detection accuracy under extreme lighting conditions. The proposed system consists of a WDR dual-imaging CMOS image sensor (CIS) that simultaneously captures a general image and a WDR binary image, an image fusion model that integrates the two images to restore lost features, and an object detection model that enhances detection performance in saturated areas. Experimental results demonstrate that the WDR binary image effectively preserves object contours even in overexposed regions, while the fusion model compensates for missing details, significantly improving object detection accuracy. Additionally, the proposed system eliminates the need for image alignment between multiple sensor inputs, providing a notable advantage in processing speed, making it highly suitable for real-time object detection applications. Quantitative evaluations show that the proposed method outperforms conventional approaches in terms of entropy, edge preservation (Qabf), and mAP@50:95, achieving up to 58.2%p higher detection performance in extreme brightness conditions. These findings confirm that the proposed WDR binary image fusion and detection system offers a robust and efficient solution for object detection in challenging high-illumination environments, ensuring enhanced visibility, improved accuracy, and real-time feasibility.

We address a long-standing conflict in SS-ADC-based CMOS image sensors (CIS): correlated-double-sampling (CDS) accuracy favors high OTA gain and wide bandwidth, whereas low decision noise during A/D conversion benefits from a much narrower effective noise bandwidth (ENBW). We propose decision-window load modulation (DWLM), a column-level technique that adds a small load modulation capacitive load to the comparator output and enables it only within the predicted decision window. This time-localized pole shift preserves CDS fidelity while shrinking the in-band noise integral during the conversion instant. We develop a unified noise analysis with DWLM, derive closed-form ENBW reductions, and provide sizing rules for the load modulation capacitive load under delay constraints and redundancy. Compared with oversampling/multi-sampling approaches, DWLM achieves measurable TN reduction without extra cycles, and remains compatible with Correlated Multiple Sampling (CMS) for additional averaging. A$640\times 480$prototype fabricated in 180-nm CMOS integrates column-parallel 10-bit SS-ADCs with dual-stage DWLM. Under dark conditions, the proposed scheme lowers temporal noise by 27.21% at$\times 1$gain and 20.04% at$\times 16$gain. The proposed design achieves competitive figures of merit:$1.811~\text {mV}_{\text {rms}}\cdot \text {nJ/pixels}$, and$1.768~\text {mV}_{\text {rms}}\cdot \text {pJ/(pixels} \cdot \text {lsb)}$, indicating the superior performance compared to state-of-the-art designs.

This paper presents a novel column-wise multi-gain high dynamic range (HDR) CMOS image sensor (CIS) designed to adapt dynamically to varying illumination conditions. The proposed CIS employs a dual ramp generator and column-parallel gain control to enable two-stage analog gain (AG) adjustments, achieving up to 256 unique column-wise gain patterns. Additionally, this study introduces an innovative image synthesis method, which allows for HDR implementation without any loss of image resolution during the synthesis process. This ensures that the sensor maintains high-resolution imaging quality while adapting dynamically to illumination changes. These innovations allow for fine-grained HDR image synthesis within a single frame, eliminating motion blur and supporting real-time performance in dynamic environments. By combining these features, the proposed approach achieves a balance between high adaptability and high-quality imaging, meeting the stringent requirements of modern machine vision systems. Fabricated using a$0.11~\mu $m CMOS process, the prototype CIS integrates a$1280\times 720$pixel array, operates at 30 fps, and consumes 4.89 mW of power. The design achieved competitive figures of merit: 176.9 pJ/frame/pixel, 15.39$\text{mV}_{\mathrm {rms}}\cdot $pJ/frame/pixel, and 0.015$\text{mV}_{\mathrm {rms}}\cdot $pJ/frame/pixel/$2^{\mathrm {N}}$. The experimental results validate the effectiveness of the column-wise multi-gain HDR approach.