This Special Issue of IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I) includes papers presented at the IEEE Latin American Symposium on Circuits and Systems (LASCAS). This annual symposium provides a high-quality exchange and networking forum for researchers, professionals, and students, gathering an international audience with experts from all over the world. The symposium is a space where the Circuits and Systems (CAS) community can present new concepts and innovative approaches, learn about new trends and solutions, and receive feedback from specialists in diverse fields. The 14th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023) was held in person from February 28 to March 3 in Quito, Ecuador. A subset of top-rated papers was selected for this Special Issue among all the contributions presented at the conference in poster and oral sessions. The invited papers brought new technical results and underwent a peer-review process consisting of expert reviewers on the related topics. A brief description of the two selected papers is as follows.

Single Event Transient (SET) faults are more notable every day at Earth applications. Even considering FinFET technology, the effects are not negligible. A circuit-level evaluation of radiation effects must consider each internal node of the cells, input vectors, particle type, and pulse width derived from the particle collision to determine the sensibility of the circuit under evaluation. Moreover, circuit characterization is time-consuming, involving many electrical simulations to reach an appropriate precision, mainly considering together with the process variability effects. This work evaluates how process variability and gate mapping impacts the radiation robustness on circuits composed by multigate devices in 7 nm FinFET technology. Firstly, the NAND2 and NOR2 gates are evaluated at nominal conditions and considering the process variability impact on the radiation sensitivity. After that, three different topologies of the same circuit are analyzed, showing that even when considering process variability, the circuit's robustness is highly dependent on its output gates and that the most sensitive part of a circuit may vary given process variability. Results also show that the$\mathbf{LET}_{th}$value may vary by order of magnitude due to the work-function fluctuation of NMOS and PMOS devices.

Advanced technologies introduce new challenges as higher process variability impact and tight power constraints, mainly for IoT applications. Schmitt Trigger inverters are traditionally used for noise immunity enhancement due to their hysteresis characteristic, and have been recently applied to mitigate radiation effects and process variability impact. Alongside, Stacked-Inverter Gates are applied for gain increase, consequently, robustness enhancement as well. Thus, the main contribution of this paper is to investigate the relationship between transistor sizing, supply voltage, energy, and process variability robustness to get a minimal energy consumption circuit with FinFET technology, while keeping robustness and to identify the recommended circuit for different applications. Results show that adjusting the supply voltage and transistor sizing, at a high variability scenario, it is possible to decrease the energy consumption up to 32.19% while maintaining adequate robustness. It was possible to show a considerable difference concerning the Schmitt Trigger noise-immunity characteristics, in comparison to other designs, over supply voltage and variability scaling.

Challenges were introduced in integrated circuits design due to the technology scaling. The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability, which can lead to circuits operating outside their specification ranges. Transistor arrangement influences the performance of logic cells; complex logic gates can be used to minimize area, delay and power. However, with the increasing relevance of nanometer challenges, it is necessary also to consider these factors at logic level design. This work explores different transistor arrangements for a set of logic functions at the layout level to evaluate the SET response under the process variability. The complex gate and the multi-level of NAND2 topologies, that implement the same function, were designed using the 7nm FinFET ASAP7 Process Design Kit. Results show that the multi-level topology is more robust to the radiation effects at both nominal conditions and considering the impact of process variability. The LETth value considering the multi-level topology is on average 55% higher than the values considering the complex topology. Moreover, all the logic functions analyzed independently of the topology are more sensitive to the SETs considering the impact of the process variability.

The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability. Traditionally, complex gates are adopted to reduce area, delay and power consumption. However, they can introduce challenges related to a robustness that might be avoided with more regular and basic cells. This extended abstract presents my current research works. Firstly, the different works performed in my research are described. Then, a short version methodology and the main results are presented.

The emergence of IoT alongside with the increased process variability impact in modern technology nodes, is the main reason to control variability impact over metrics. Given the large set of IoT devices working in battery-oriented environments, energy consumption should be minimal and the operation regime reliable. Schmitt Trigger inverters are traditionally used for noise immunity enhancement, and have been recently applied to mitigate radiation effects and process variability impact. However, Schmitt Trigger operation at the nominal voltage introduces high degradation on power consumption. Thus, the main contribution of this paper is to identify the relationship between transistor sizing, supply voltage, energy, and process variability robustness to get a minimal energy consumption circuit while keeping robustness. The results are extracted from 7-nm FinFET Schmitt Trigger layouts under different levels of process variability, supply voltages, and sizing. Also, a maximum frequency scaling under a failure threshold was performed. On average, the supply voltage decreases in layouts with a smaller number of fins, while maintaining acceptable robustness in high variability scenarios. Exploring voltage and transistor sizing made possible a reduction of about 24.84% of power consumption.

With battery-oriented applications rising in IoT, alongside the challenge of supplying electrical power, a reliable energy consumption metric must be satisfied. Although, variability has emerged as one of the critical threats to reliable metrics making the development of robustness techniques necessary. Schmitt Trigger Inverters haye been applied in designs due to its hysteresis characteristic, improving robustness. Still, Schmitt Triggers at nominal values of supply voltage may cause high degradation on power consumption. Thus, this work aims to indicate the appropriate dimensioning and supply voltage value for minimum energy consumption whOe preserving adequate robustness. It was found that the appropriate dimensioning and supply voltage can reduce up to 26.31% energy consumption.

The yield optimization and radiation hardness are relevant reliability requirements as chip manufacturing advances more in-depth into the nanometer regime. One way to obtain improvements in these issues is by applying techniques to mitigate the effects of process variability and radiation-induced soft errors in the circuits. This work reports the use of three circuit-level approaches in FinFET designs as well as point out the pros and cons of adopting it.

This paper evaluates the benefits and drawbacks of using Schmitt Trigger (ST) inverters to minimize process, voltage and temperature variability effects on full adders. Variability mainly affects the energy outcomes on full adders, and the use of ST techniques can decrease up to 80% the energy deviation. However, it implies in a significant increase on the energy consumption. Considering the pros and cons, Mirror CMOS FA is the most beneficiated with the ST inverters, with a small impact on the average delay and a significant reduction in the energy and delay deviation.

The high integration capacity of digital circuits, which occurs due to technological scaling, presents new challenges for nanotechnology designs. The evolution of integrated circuits has made them more susceptible to faults, besides increasing the process variability, which can lead to circuits operating outside their specification ranges. This work evaluates the effects of process variability and radiation faults on complex gates. These effects are compared to alternative circuits that implement the same functions but exploring a multi-level of basic cells as NAND2, NOR2 and Inverters. The technology adopted is 7nm FinFET ASAP. Results show that although complex cells present better timing and power results, multi-level circuits are up to 28% less sensible to radiation faults and about 40% more stable under process variability.

This work provides a detailed set of predictive data about FinFET and Trigate devices behavior considering process variability effects in ON and OFF currents. These evaluations help to understand the impact of variability sources identifying relevant behavior standards with respect to the use of FinFET and Trigate devices. The IOFFsuffers the higher impact of geometric variability, mainly on FinFET devices. PFET devices and the LSTP model are also more sensitive than NFET devices and high performance models. Results highlights that Trigate devices are up to 10% less sensitive to gate length variations.

This paper investigates the impact of the main sources of variation on performance and power consumption for different transistor sizing techniques applied to cells in FinFET technologies. The analysis considers process, voltage and temperature variations, individually. Voltage and temperature variations are combined to obtain an insight into their contributions. Results are useful to define the variability contributions in the early design steps and to select the most appropriate transistor sizing technique for a targeted application. Results provide a quantitative understanding of each contribution considering a 14nm FinFET technology.