EDBT 2026 Demo / reviewers in the wild / expert
Siam U. Hussain
dblp:154/2953 · also Siam Umar Hussain
· DBLP profile ↗
13ranked-venue papers
7as first author
2since 2021 · last 2024
0000-0001-8668-0702ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 11 · 6 first-author · 1 since 2021Security and privacy · 2 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
7 papers |
Cryptographic protocols and secure computation · 55% Privacy and data protection · 34% Hardware security and side channels · 12% | |
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Hardware accelerators and domain-specific architectures · 47% Electronic design automation · 25% Reconfigurable computing and FPGAs · 19% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 16 heaviest of 19, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cryptographic protocols and secure computation
garbled circuits |
1.0 | 5 | 2019 | ARM2GC: Succinct Garbled Processor for Secure Computation · DAC 2019 TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits · IEEE Symposium on Security and Privacy 2015 Compacting privacy-preserving k-nearest neighbor search using logic synthesis · DAC 2015 |
Privacy and data protection
privacy-preserving machine learning |
0.5 | 1 | 2021 | COINN: Crypto/ML Codesign for Oblivious Inference via Neural Networks · CCS 2021 |
Cryptographic protocols and secure computation
secure inference |
0.5 | 1 | 2021 | COINN: Crypto/ML Codesign for Oblivious Inference via Neural Networks · CCS 2021 |
Cryptographic protocols and secure computation › secure inference
secure neural network inference |
0.5 | 1 | 2021 | COINN: Crypto/ML Codesign for Oblivious Inference via Neural Networks · CCS 2021 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.5 | 2 | 2021 | MAXelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud servers · DAC 2018 COINN: Crypto/ML Codesign for Oblivious Inference via Neural Networks · CCS 2021 |
Privacy and data protection
privacy-enhancing technologies |
0.4 | 1 | 2020 | Developing Privacy-preserving AI Systems: The Lessons learned · DAC 2020 |
Electronic design automation
logic synthesis |
0.4 | 2 | 2015 | TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits · IEEE Symposium on Security and Privacy 2015 Compacting privacy-preserving k-nearest neighbor search using logic synthesis · DAC 2015 |
Hardware security and side channels › trusted execution environments
secure processor |
0.4 | 1 | 2019 | ARM2GC: Succinct Garbled Processor for Secure Computation · DAC 2019 |
Reconfigurable computing and FPGAs
FPGA accelerator |
0.3 | 1 | 2018 | MAXelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud servers · DAC 2018 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › trustworthy machine learning accelerator
privacy-preserving machine learning accelerator |
0.3 | 1 | 2018 | MAXelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud servers · DAC 2018 |
Privacy and data protection
location privacy |
0.2 | 1 | 2016 | Privacy preserving localization for smart automotive systems · DAC 2016 |
Privacy and data protection › location privacy
privacy-preserving localization |
0.2 | 1 | 2016 | Privacy preserving localization for smart automotive systems · DAC 2016 |
Cryptographic protocols and secure computation › secure multiparty computation
private function evaluation |
0.2 | 1 | 2015 | TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits · IEEE Symposium on Security and Privacy 2015 |
GPUs and heterogeneous computing › GPU computing
cryptographic acceleration |
0.1 | 1 | 2021 | COINN: Crypto/ML Codesign for Oblivious Inference via Neural Networks · CCS 2021 |
Cryptographic protocols and secure computation
secure multiparty computation |
0.1 | 1 | 2020 | Developing Privacy-preserving AI Systems: The Lessons learned · DAC 2020 |
Hardware security and side channels
trusted execution environments |
0.1 | 1 | 2020 | Developing Privacy-preserving AI Systems: The Lessons learned · DAC 2020 |
Methods — techniques the papers use, named apart from their topics
yao's garbled circuit · 1.6secure multiparty computation · 1.4homomorphic encryption · 1.4quantization · 1.0logic synthesis · 0.9skipgate · 0.8ARM compilation · 0.8sequential circuit synthesis · 0.4garbling frameworks · 0.4trusted execution environment · 0.4sequential circuit optimization · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Scalable Binary Neural Network Applications in Oblivious InferenceabstractBinary neural network (BNN) delivers increased compute intensity and reduces memory/data requirements for computation. Scalable BNN enables inference in a limited time due to different constraints. This paper explores the application of Scalable BNN in oblivious inference, a service provided by a server to mistrusting clients. Using this service, a client can obtain the inference result on his/her data by a trained model held by the server without disclosing the data or learning the model parameters. Two contributions of this paper are: (1) we devise lightweight cryptographic protocols explicitly designed to exploit the unique characteristics of BNNs. (2) we present an advanced dynamic exploration of the runtime-accuracy tradeoff of scalable BNNs in a single-shot training process. While previous works trained multiple BNNs with different computational complexities (which is cumbersome due to the slow convergence of BNNs), we train a single BNN that can perform inference under various computational budgets. Compared to CryptFlow2, the state-of-the-art technique in the oblivious inference of non-binary DNNs, our approach reaches 3× faster inference while keeping the same accuracy. Compared to XONN, the state-of-the-art technique in the oblivious inference of binary networks, we achieve 2× to 12× faster inference while obtaining higher accuracy. Xinqiao Zhang, Mohammad Samragh Razlighi, Siam U. Hussain, Ke Huang 0001, Farinaz Koushanfar |
ACM Trans. Embed. Comput. Syst. | 3 |
| 2021 | COINN: Crypto/ML Codesign for Oblivious Inference via Neural NetworksabstractWe introduce COINN - an efficient, accurate, and scalable framework for oblivious deep neural network (DNN) inference in the two-party setting. In our system, DNN inference is performed without revealing the client's private inputs to the server or revealing server's proprietary DNN weights to the client. To speedup the secure inference while maintaining a high accuracy, we make three interlinked innovations in the plaintext and ciphertext domains: (i) we develop a new domain-specific low-bit quantization scheme tailored for high-efficiency ciphertext computation, (ii) we construct novel techniques for increasing data re-use in secure matrix multiplication allowing us to gain significant performance boosts through factored operations, and (iii) we propose customized cryptographic protocols that complement our optimized DNNs in the ciphertext domain. By co-optimization of the aforesaid components, COINN brings an unprecedented level of efficiency to the setting of oblivious DNN inference, achieving an end-to-end runtime speedup of 4.7×14.4× over the state-of-the-art. We demonstrate the scalability of our proposed methods by optimizing complex DNNs with over 100 layers and performing oblivious inference in the Billion-operation regime for the challenging ImageNet dataset. Our framework is available at https://github.com/ACESLabUCSD/COINN.git. Siam U. Hussain, Mojan Javaheripi, Mohammad Samragh Razlighi, Farinaz Koushanfar |
CCS | 1 |
| 2020 | Developing Privacy-preserving AI Systems: The Lessons learnedabstractAdvances in customers' data privacy laws create pressures and pain points across the entire lifecycle of AI products. Working figures such as data scientists and data engineers need to account for the correct use of privacy-enhancing technologies such as homomorphic encryption, secure multi-party computation, and trusted execution environment when they develop, test and deploy products embedding AI models while providing data protection guarantees. In this work, we share the lessons learned during the development of frameworks to aid data scientists and data engineers to map their optimized workloads onto privacy-enhancing technologies seamlessly and correctly. Huili Chen, Siam U. Hussain, Fabian Boemer, Emmanuel Stapf, Ahmad-Reza Sadeghi, Farinaz Koushanfar, Rosario Cammarota |
DAC | 2 |
| 2019 | ARM2GC: Succinct Garbled Processor for Secure ComputationabstractWe present ARM2GC, a novel secure computation framework based on Yao's Garbled Circuit (GC) protocol and the ARM processor. It allows users to develop privacy-preserving applications using standard high-level programming languages (e.g., C) and compile them using off-the-shelf ARM compilers, e.g., gcc-arm. The main enabler of this framework is the introduction of SkipGate, an algorithm that dynamically omits the communication and encryption cost of a gate when its output is independent of the private data. SkipGate greatly enhances the performance of ARM2GC by omitting costs of the gates associated with the instructions of the compiled binary, which is known by both parties involved in the computation. Our evaluation on benchmark functions demonstrates that ARM2GC outperforms the prior best solution by 156×. Ebrahim M. Songhori, M. Sadegh Riazi, Siam U. Hussain, Ahmad-Reza Sadeghi, Farinaz Koushanfar |
DAC | 3 |
| 2019 | FASE: FPGA Acceleration of Secure Function EvaluationabstractWe present FASE, an FPGA accelerator for Secure Function Evaluation (SFE) by employing the well-known cryptographic protocol named Yao's Garbled Circuit (GC). SFE allows two parties to jointly compute a function on their private data and learn the output without revealing their inputs to each other. FASE is designed to allow cloud servers to provide secure services to a large number of clients in parallel while preserving the privacy of the data from both sides. Current SFE accelerators either target specific applications, and therefore are not amenable to generic use, or have low throughput due to inefficient management of resources. In this work, we present a pipelined architecture along with an efficient scheduling scheme to ensure optimal usage of the available resources. The scheme is built around a simulator of the hardware design that schedules the workload and assigns the most suitable task to the encryption cores at each cycle. This, coupled with optimal management of the read and write cycles of the Block RAM on FPGA, results in a minimum 2 orders of magnitude improvement in terms of throughput per core for the reported benchmarks compared to the most recent generic GC accelerator. Moreover, our encryption core requires 17% less resource compared to the most recent secure GC realization. Siam U. Hussain, Farinaz Koushanfar |
FCCM | 1 |
| 2018 | MAXelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud serversabstractThis paper presents MAXelerator, the first hardware accelerator for privacy-preserving machine learning (ML) on cloud servers. Cloud-based ML is being increasingly employed in various data sensitive scenarios. While it enhances both efficiency and quality of the service, it also raises concern about privacy of the users' data. We create a practical privacy-preserving solution for matrix-based ML on cloud servers. We show that for the majority of the ML applications, the privacy-sensitive computation boils down to either matrix multiplication, which is a repetition of Multiply-Accumulate (MAC) or the MAC itself. We design an FPGA architecture for privacy-preserving MAC to accelerate the ML computation based on the well known Secure Function Evaluation protocol named Yao's Garbled Circuit. MAXelerator demonstrates up to 57× improvement in throughput per core compared to the fastest existing GC framework. We corroborate the effectiveness of the accelerator with real-world case studies in privacy-sensitive scenarios. Siam U. Hussain, Bita Darvish Rouhani, Mohammad Ghasemzadeh 0002, Farinaz Koushanfar |
DAC | 1 |
| 2018 | P3: Privacy Preserving Positioning for Smart Automotive SystemsabstractThis article presents the first privacy-preserving localization method based on provably secure primitives for smart automotive systems. Using this method, a car that is lost due to unavailability of GPS can compute its location with assistance from three nearby cars, while the locations of all the participating cars including the lost car remain private. Technological enhancement of modern vehicles, especially in navigation and communication, necessitates parallel enhancement in security and privacy. Previous approaches to maintaining user location privacy suffered from one or more of the following drawbacks: trade-off between accuracy and privacy, one-sided privacy, and the need of a trusted third party that presents a single point to attack. The localization method presented here is one of the very first location-based services that eliminates all these drawbacks. Two protocols for computing the location is presented here based on two Secure Function Evaluation (SFE) techniques that allow multiple parties to jointly evaluate a function on inputs that are encrypted to maintain privacy. The first one is based on the two-party protocol named Yao’s Garbled Circuit (GC). The second one is based on the Beaver-Micali-Rogaway (BMR) protocol that allows inputs from more than two parties. The two secure localization protocols exhibit trade-offs between performance and resilience against collusion. Along with devising the protocols, we design and optimize netlists for the functions required for location computation by leveraging conventional logic synthesis tools with custom libraries optimized for SFE. Proof-of-concept implementation of the protocol shows that the complete operation can be performed within only 355ms. The fast computing time enables localization of even moving cars. Siam U. Hussain, Farinaz Koushanfar |
ACM Trans. Design Autom. Electr. Syst. | 1 |
| 2018 | SHAIP: Secure Hamming Distance for Authentication of Intrinsic PUFsabstractIn this article, we present SHAIP, a secure Hamming distance–based mutual authentication protocol. It allows an unlimited number of authentications by employing an intrinsic Physical Unclonable Function (PUF). PUFs are being increasingly employed for remote authentication of devices. Most of these devices have limited resources. Therefore, the intrinsic PUFs are most suitable for this task as they can be built with little or no modification to the underlying hardware platform. One major drawback of the current authentication schemes is that they expose the PUF response. This makes the intrinsic PUFs, which have a limited number of challenge-response pairs, unusable after a certain number of authentication sessions. Moreover, these schemes are one way in the sense that they only allow one party, the prover, to authenticate herself to the verifier. We propose a symmetric mutual authentication scheme based on secure (privacy-preserving) computation of the Hamming distance between the PUF response from the remote device and reference response stored at the verifier end. This allows both parties to authenticate each other without revealing their respective sets of inputs. We show that our scheme is effective with all state-of-the-art intrinsic PUFs. The proposed scheme is lightweight and does not require any modification to the underlying hardware. Siam U. Hussain, M. Sadegh Riazi, Farinaz Koushanfar |
ACM Trans. Design Autom. Electr. Syst. | 1 |
| 2018 | ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in Clouds Using FPGAsabstractArtificial Intelligence (AI) is increasingly incorporated into the cloud business in order to improve the functionality (e.g., accuracy) of the service. The adoption of AI as a cloud service raises serious privacy concerns in applications where the risk of data leakage is not acceptable. Examples of such applications include scenarios where clients hold potentially sensitive private information such as medical records, financial data, and/or location. This article proposes ReDCrypt, the first reconfigurable hardware-accelerated framework that empowers privacy-preserving inference of deep learning models in cloud servers. ReDCrypt is well-suited for streaming (a.k.a., real-time AI) settings where clients need to dynamically analyze their data as it is collected over time without having to queue the samples to meet a certain batch size. Unlike prior work, ReDCrypt neither requires to change how AI models are trained nor relies on two non-colluding servers to perform. The privacy-preserving computation in ReDCrypt is executed using Yao’s Garbled Circuit (GC) protocol. We break down the deep learning inference task into two phases: (i) privacy-insensitive (local) computation, and (ii) privacy-sensitive (interactive) computation. We devise a high-throughput and power-efficient implementation of GC protocol on FPGA for the privacy-sensitive phase. ReDCrypt’s accompanying API provides support for seamless integration of ReDCrypt into any deep learning framework. Proof-of-concept evaluations for different DL applications demonstrate up to 57-fold higher throughput per core compared to the best prior solution with no drop in the accuracy. Bita Darvish Rouhani, Siam U. Hussain, Kristin E. Lauter, Farinaz Koushanfar |
ACM Trans. Reconfigurable Technol. Syst. | 2 |
| 2016 | Privacy preserving localization for smart automotive systemsabstractThis paper presents the first provably secure localization method for smart automotive systems. Using this method, a lost car can compute its location with assistance from three nearby cars while the locations of all the participating cars including the lost car remain private. This localization application is one of the very first location-based services that does not sacrifice accuracy to maintain privacy. The secure location is computed using a protocol utilizing Yao's Garbled Circuit (GC) that allows two parties to jointly compute a function on their private inputs. We design and optimize GC netlists of the functions required for computation of location by leveraging conventional logic synthesis tools. Proof-of-concept implementation of the protocol shows that the complete operation can be performed within only 550 ms. The fast computing time enables practical localization of moving cars. Siam U. Hussain, Farinaz Koushanfar |
DAC | 1 |
| 2015 | Compacting privacy-preserving k-nearest neighbor search using logic synthesisabstractThis paper introduces the first efficient, scalable, and practical method for privacy-preserving k-nearest neighbors (k-NN) search. The approach enables performing the widely used k-NN search in sensitive scenarios where none of the parties reveal their information while they can still cooperatively find the nearest matches. The privacy preservation is based on the Yao's garbled circuit (GC) protocol. In contrast with the existing GC approaches that only accept function descriptions as combinational circuits, we suggest using sequential circuits. This work introduces novel transformations, such that the sequential description can be evaluated by interfacing with the existing GC schemes that only accept combinational circuits. We demonstrate a great efficiency in the memory required for realizing the secure k-NN search. The first-of-a-kind implementation of privacy preserving k-NN, utilizing the Synopsys Design Compiler on a conventional Intel processor demonstrates the applicability, efficiency, and scalability of the suggested methods. Ebrahim M. Songhori, Siam U. Hussain, Ahmad-Reza Sadeghi, Farinaz Koushanfar |
DAC | 2 |
| 2015 | TinyGarble: Highly Compressed and Scalable Sequential Garbled CircuitsabstractWe introduce Tiny Garble, a novel automated methodology based on powerful logic synthesis techniques for generating and optimizing compressed Boolean circuits used in secure computation, such as Yao's Garbled Circuit (GC) protocol. Tiny Garble achieves an unprecedented level of compactness and scalability by using a sequential circuit description for GC. We introduce new libraries and transformations, such that our sequential circuits can be optimized and securely evaluated by interfacing with available garbling frameworks. The circuit compactness makes the memory footprint of the garbling operation fit in the processor cache, resulting in fewer cache misses and thereby less CPU cycles. Our proof-of-concept implementation of benchmark functions using Tiny Garble demonstrates a high degree of compactness and scalability. We improve the results of existing automated tools for GC generation by orders of magnitude, for example, Tiny Garble can compress the memory footprint required for 1024-bit multiplication by a factor of 4,172, while decreasing the number of non-XOR gates by 67%. Moreover, with Tiny Garble we are able to implement functions that have never been reported before, such as SHA-3. Finally, our sequential description enables us to design and realize a garbled processor, using the MIPS I instruction set, for private function evaluation. To the best of our knowledge, this is the first scalable emulation of a general purpose processor. Ebrahim M. Songhori, Siam U. Hussain, Ahmad-Reza Sadeghi, Thomas Schneider 0003, Farinaz Koushanfar |
IEEE Symposium on Security and Privacy | 2 |
| 2014 | BIST-PUF: online, hardware-based evaluation of physically unclonable circuit identifiersabstractPhysical Unclonable Functions (PUF) are of increasing importance due to their many hardware security applications including chip fingerprinting, metering, authentication, anti-counterfeiting, and supply-chain tracing, e.g., DARPA SHIELD. This paper presents BIST-PUF, the first built-in-self-test (BIST) methodology for online evaluation of weak and strong PUFs. BIST-PUF provides a paradigm shift in the evaluation of the un-clonable circuit identifiers: unlike earlier known PUF evaluation suites that are software-based and offline, BIST-PUF enables on-the-fly assessment of the desired PUF properties all in hardware. More specifically, the BIST-PUF structure is designed to evaluate two main properties of PUFs, namely unpredictability and stability. These properties are important for ensuring robustness and security in face of operational, structural, and environmental fluctuations due to variations, aging or adversarial acts. For BIST-PUF unpredictability evaluation, we identify and adopt the tests of randomness that are amenable to hardware implementation. For stability assessment, the BIST-PUF suggests three distinct methods, namely, sensor-based, parametric interrogation, and multiple interrogations. Proof-of-concept implementation of the BIST-PUF in FPGA demonstrates its low overhead, effectiveness, and practicality. Siam U. Hussain, Sudha Yellapantula, Mehrdad Majzoobi, Farinaz Koushanfar |
ICCAD | 1 |