Recent advances in CMOS technology have enabled the implementation of high-performance and energy-efficient digital-intensive radio transceivers for fifth-generation (5G) and beyond (6G) wireless communication systems. Among the various transmitter architectures, the outphasing transmitter with constant-amplitude modulation, which allows the use of highly energy-efficient nonlinear power amplifiers, has garnered significant attention since it easily lends itself to a digital-intensive implementation, thus fully exploiting the benefits of scaled CMOS technologies. However, an outphasing transmitter with a delay-based phase modulator suffers from performance degradation due to mismatch-induced static nonlinearity. This paper presents a linearization algorithm that minimizes mismatch-induced static nonlinearity by reordering the unary-weighted delay elements. The effectiveness of this algorithm is demonstrated through simulations and its application to measured delay characteristics from a 22-nm FDSOI CMOS transmitter prototype in a system simulation. The proposed reordering algorithm results in a 7.94% points improvement from 10.63% in EVM and a 7.76dB enhancement from 25dB in ACLR for a 5G NR 64-QAM OFDM waveform with a 200MHz bandwidth.

The digital front-end of the communication transceivers envisioned for fifth-generation (5G) and beyond requires highly configurable high-performance digital signal processing (DSP) hardware operating at very high sampling rates to accommodate increasing signal bandwidths and support a range of modulation schemes and transmitter architectures. In this article, we present an efficient implementation of a highly configurable DSP hardware generator that can generate high-performance DSP hardware for multiple transmitter architectures including Cartesian, polar, outphasing, and multilevel outphasing modulators. The generated hardware unit, which consists of multistage multirate filters and other required DSP operations, runs at sample rates up to 4 GHz. The hardware supports an adjacent channel leakage ratio (ACLR) down to −48 dB and an error vector magnitude (EVM) of 0.78% with a 7-bit phase signal at a sampling rate of 4 GHz for multilevel outphasing modulation. Digital synthesis of the circuit in a 5-nm complimentary metal-oxide semiconductor (CMOS) process yields a core area consumption of 0.01 mm2 and an estimated power consumption of 37.2 mW for a 200-MHz bandwidth 5G new radio (NR) baseband (BB) signal.

In this article, we comprehensively investigate the potential of the digital polar radio transmitter architecture for multi-user massive multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) downlink system. In terms of throughput performance, we derive a lower bound for the average sum-rate achievable with Gaussian signaling inputs and zero-forcing (ZF) precoding based on Bussgang decomposition. By diagonal approximation, we derive an approximate, yet accurate, model for the distortion caused by uniform polar quantization, which can be used to evaluate the corresponding sum-rate in closed form. To assess the power efficiency, we provide power consumption models with realistic parameters and values for the quantized polar and Cartesian transmitters, based on state-of-the-art integrated circuit (IC) designs and measurements. Extensive numerical results demonstrate that the proposed quantized polar transmitter can enable excellent performance in terms of average sum-rate, symbol error rate (SER), and out-of-band (OOB) emission level, compared to the Cartesian architecture. Furthermore, the power consumption comparisons show that the digital polar transmitter can save more than 36% in the energy consumption under 64-antenna setting in typical 5G enhanced mobile broadband use cases, thus making it highly appealing for future power-efficient massive MIMO transmitter implementations.

This article investigates the feasibility of combinerless multilevel outphasing transmitter as a potential architecture for large millimeter-wave (mmWave) phased arrays. We consider two distinct ways of distributing the component signals to the antennas and develop a model for the received signal at each radiated spatial direction from a phased array. Based on the received signal model, we derive expressions for the signal-to-distortion ratio as well as total power experienced at each spatial direction. Furthermore, antenna branch mismatches, overload distortion and quantization are considered, and an analytical model for the signal-to-distortion ratio at the intended receiver is derived. We additionally establish a model for comparing the achievable energy efficiency to those of the relevant reference methods. Extensive numerical experiments are carried out to verify the analytical works, and to assess the commonly used metrics of error vector magnitude (EVM) and total radiated power adjacent channel leakage ratio (TRP-ACLR). It is shown that the combinerless architecture is a valid option for mmWave phased arrays, demonstrating favorable EVM results and TRP-ACLR beyond the 28 dBc limit imposed by the 3GPP, even in the presence of the considered distortions. The conducted energy efficiency assessment shows that efficiency of the reference methods can be exceeded with sufficient amount of outphasing levels. The considered architecture is thus an interesting alternative for addressing the linearity vs. energy-efficiency challenge in mmWave phased-array systems.

Cyclic-coupled ring oscillators (CCRO), which consist of M ring oscillators each with N inverting stages, can be used in time-domain data converters to achieve sub-gate-delay resolution and improved phase noise performance compared to a single ring oscillator (RO). However, CCROs can oscillate in several different oscillation modes, where some modes contain overlapping phases. Such in-phase oscillations severely degrade the performance of a time-domain data converter by undermining the sub-gate-delay of the CCRO. This paper presents a design method to avoid the undesired in-phase oscillation modes, and thus achieve guaranteed maximal phase resolution regardless of the oscillation mode, by properly selecting the CCRO dimensions N and M. We show, both theoretically and with transistor-level simulations, that mode-agnostic maximum phase resolution can be ensured by selecting a prime M together with an N which is co-prime with M.

Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismatch is realized with analog delay lines, making it challenging for high-speed ADC designs to achieve fine delay resolution over wide tuning range while maintaining low clock jitter. Digital skew correction allows greater flexibility than analog solutions, but is hindered by a significant hardware footprint. This paper demonstrates digital filter-based timing skew correction approach suitable for on-chip implementation. In a 10-bit 8-channel TI-ADC the proposed structure corrects mismatch magnitudes up to 0.12 sample period across 0.9 Nyquist band while requiring only 65% hardware of similar architectures of equivalent performance. The presented digital circuit uses reduced combinational paths and operates at a clock rate of single ADC channel, making it applicable for digitally-assisted high-speed TI-ADCs.

An integrated circuit that measures time intervals with high precision and accuracy has a wide range of applications including data conversion, ranging, and 3-D imaging. The resolution with which time intervals are quantized by a ring oscillator or delay line is limited by the minimum delay of an inverter in the technology. We propose the use of cyclic-coupled ring oscillators (CCROs) as a time-domain quantizer to achieve a combination of subgate-delay time resolution together with a short conversion time, thereby enabling data conversion with high resolution as well as high bandwidth. The resolution-power tradeoff in coupled oscillators is studied. Simulation indicates up to a factor-of-13 subgate-delay time resolution with 13 coupled oscillators. A real-time quantizing time-to-digital converter with coupled oscillators is designed for a time-domain analog-to-digital converter. Powered by a factor-of-8 subgate-delay time resolution of 1.6 ps obtained with nine coupled oscillators, and a sample time of 4 ns for 11-bit conversion, the converter delivers a 9.9-bit ENOB over a signal bandwidth of 125 MHz and an SFDR of 88 dB. Results demonstrate that CCROs is an attractive candidate as a high-precision high-linearity time-domain quantizer for data converters.

A digital-friendly approach to implement injection-locked ring oscillators is proposed. We show that lock can be achieved by dynamically switching the delay of a delay element in a ring oscillator. A logic gate that generates the control signal for switching the delay, together with a one-bit controlled oscillator, inherently realizes a locking mechanism. Measurement results from a prototype circuit fabricated with a 28 nm CMOS process demonstrate the feasibility of the concept. The circuit with a measured lock range of 2.4-3.7 GHz occupies an area of 0.00043 mm2and consumes 0.18 mW power.