In recent years, the development of smart edge computing systems to process information locally is on the rise. Many near-sensor machine learning (ML) approaches have been implemented to introduce accurate and energy efficient template matching operations in resource-constrained edge sensing systems, such as wearables. To introduce novel solutions that can be viable for extreme edge cases, hybrid solutions combining conventional and emerging technologies have started to be proposed. Deep Neural Networks (DNN) optimised for edge application alongside new approaches of computing (both device and architecture -wise) could be a strong candidate in implementing edge ML solutions that aim at competitive accuracy classification while using a fraction of the power of conventional ML solutions. In this work, we are proposing a hybrid software-hardware edge classifier aimed at the extreme edge near-sensor systems. The classifier consists of two parts: (i) an optimised digital tinyML network, working as a front-end feature extractor, and (ii) a back-end RRAM-CMOS analogue content addressable memory (ACAM), working as a final stage template matching system. The combined hybrid system exhibits a competitive trade-off in accuracy versus energy metric with$E_{front-end}$=$96.23 nJ$and$E_{back-end}$=$1.45 nJ$for each classification operation compared with 78.06 μJ for the original teacher model, representing a 792-fold reduction, making it a viable solution for extreme edge applications.

The computational bottlenecks encountered for memory access and data transfer in modern computing systems, especially for edge computing, require innovations both at device level and architectural level. Emerging technologies, like Resistive RAM (RRAM), can be used to develop novel analogue circuits and systems used to perform cornerstone machine learning operations in the analogue domain, without requiring data conversion in edge applications. In this work, we present RRAM-based artificial neurons used to implement Gaussian Activation Functions (GAFs) aimed at energy efficient analogue Radial Basis Function NNs (RBFNNs) implementation. We are show-casing a configurable RRAM-CMOS circuit emulating GAF-based neuron designed using a commercially available 180nm CMOS technology and in-house RRAM model, operated at 3.3V and 100MHz while dissipating 140fJ per cell per operation. We aim at using this cell as building block for designing a proof-of-concept memory-centric edge classifier. Through the capability of processing analogue information, the circuit can be used to process analogue information in near-sensor computing paradigms.

In this demonstration, we present a hardware/software co-design methodology for Convolutional Neural Networks, where the classification section is managed through Resistive RAMs (RRAMs). To this aim, RRAM arrays are mounted onto the ArC TWO instrumentation board, which is interfaced to a laptop. A software Python front-end executes convolutional layers for feature extraction, generates stimuli for RRAMs, and controls the instrumentation board. As a proof of concept, handwritten digits classification is exhibited.

The continuous shift of computational bottlenecks to the memory access and data transfer, especially for AI applications, poses the urgent needs of re-engineering the computer architecture fundamentals. Many edge computing applications, like wearable and implantable medical devices, introduce increasingly more challenges to conventional computing systems due to the strict requirements of area and power at the edge. Emerging technologies, like Resistive RAM (RRAM), have shown a promising momentum in developing neuro-inspired analogue computing paradigms capable of achieving high classification capabilities alongside high energy efficiency. In this work, we present a novel RRAM-based Analogue Content Addressable Memory (ACAM) for on-line analogue template matching applications. This ACAM-based template matching architecture aims to achieve energy-efficient classification where low energy is of utmost importance. We are showcasing a highly tuneable novel RRAM-based ACAM pixel implemented using a commercial 180 nm CMOS technology and in-house RRAM technology and exhibiting low energy dissipation of approximately 0.036 pJ and 0.16 pJ for mismatch and match, respectively, at 66 MHz with 3.3 V voltage supply. A proof-of-concept system-level implementation based on this novel pixel design is also implemented in 180 nm.

The template matching approach has a promising momentum to build energy-efficient edge classifiers for var-ious implantable and wearable medical devices. To mitigate the analog/digital cross-domain interfacing complexity, analog content-addressable memories can be used efficiently to form the back-end classifiers by receiving the analog inputs and generating the digital classification outputs. This paper presents a novel memristor-based analog content-addressable memory pixel 1TIR+2T with 2.0x smaller footprint than its counterparts in the literature. The new compact pixel utilizes only one RRAM device through a 1T1R voltage divider circuit while exploiting the complementary behavior of the nMOS and pMOS transistors to determine the lower and upper bounds of the matching voltage range. The simulation results show that the 1T1R+2T pixel has a promising tunability with matching windows range from 50 mV to 200 mV according to the RRAM resistance value of the 1T1R voltage divider.

An important cornerstone of data processing is the ability to efficiently capture structure in data and perform data classification. More recently, memristive technologies enabled the incorporation of continuous tuneable resistive elements directly in hardware, thus increasing the efficiency of reconfigurable systems power and area-wise. Memristors are a promising candidate for reconfigurable circuits capable of carrying out classification with physical computing, such as dot-product vector multiplication and accumulation technique. In this work, we demonstrate a novel proof-of-concept memristor-based Digital-In-Analogue-Out logic circuit and present preliminary results highlighting the effect of non-uniform non-linear memristor IV characteristics that result in device-to-device behavioural variation.

With the recent advances of the emerging memories technologies, research are able to implement novel circuits, systems and computer architectures towards the design of high-performance and low-power electronic systems able to accelerate and/or optimize the functionality of many computer workflows. One emerging technology, the ReRAM/memristor is gathering attention due to its inherent advantages for logic and memory computing systems. At the same time, CMOS circuit design seems to have reached a limit, where easily optimized circuit solutions cannot be found. Thus, further research towards novel logic gate families, such as Threshold Logic Gates (TLGs), a logic family known for its high-speed and low power consumption, is needed. Although many implementation concepts of TLG circuit are using memristors, few of these implementations are based on physical ReRAM devices. In this work we are proposing a memristor-based threshold logic gate design towards the optimization of computer workflows. The presented results include a physical implementation of the proposed circuits which supports the concept of memory-based reconfigurable computing circuits and systems.

An important cornerstone of data processing is the ability to efficiently capture structure in data. This entails treating the input space as a hyperplane that needs partitioning. We argue that several modern electronic systems can be understood as carrying out such partitionings: from standard logic gates to Artificial Neural Networks (ANNs). More recently, memristive technologies equipped such systems with the benefit of continuous tuneability directly in hardware, thus rendering these reconfigurable in a power and space efficient manner. Here, we demonstrate several proof-of-concept examples where memristors enable circuits optimised to carry out different flavours of the fundamental task of splitting the hyperplane. These include threshold logic and receptive field based classifiers that are presented within the context of a unified perspective.