A hybrid high-voltage regulating charge pump is proposed for point-of-care electrokinetic concentration chip applications. The hybrid charge pump is composed of three cascaded sub-pumps. High efficiency, minimized area, wide output current range, and high regulated output voltage are achieved by selecting charge pump architectures that provide high voltage conversion gain with less number of stages. The proposed charge pump is designed and fabricated in 180 nm BCD process. Simulation results show that the proposed system provides a maximum efficiency of 48.26%, while providing a maximum output voltage of 65 V.

This paper presents a high-throughput impedance readout IC with a novel synchronous cyclic integration technique using a scalable capacitive transimpedance stage. The proposed technique removes the need for the low pass filter (LPF) in the readout chain and performs the I/Q demodulation within a single cycle. Fabricated in a 180-nm CMOS process, the proposed IC consumes 50 μW from a 1.2-V supply. It can measure impedances over a frequency of 100 Hz to 100 kHz with an accuracy of 99.7% and can achieve a throughput of 50 kSps at 100 kHz input frequency.

In this paper, a fully-integrated digital low dropout (DLDO) regulator is proposed utilizing a multi-bits shift handler (MBSH), decremental-gain PMOS array, and adaptive coarse loop controller to achieve fast load transient responses with improved line and load regulations. An undershoot-limiter loop (ULL) is also proposed to help to reduce the voltage undershoot peak during load current transients. To significantly mitigate the steady-state voltage ripples (VRIPP) and quiescent current (IQ), we propose a synchronized fine-loop freezer (FLF) in the fine loop of the DLDO that is only activated when VREGgets equal to VREF. The proposed DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.22 mm2. The simulation results demonstrate that the proposed DLDO achieves ≤ 130 μV of VRIPPwhile maintaining a minimum dropout voltage of 20 mV and a peak current efficiency of 99.96 %.

This paper presents a neural recording integrated circuit (IC) with a DC-coupled VCO-based continuous-time ΔΣ modulator with a novel input transistor ΔΣ digital-to-analog converter (DAC) technique. The input transistor operating as a transconductor is implemented in the form of a transistor DAC (TR-DAC) consisting of multiple transistors, which enables the ΔΣ operation according to the output digital code. Notably, this topology isolates the input from the feedback loop, resulting in exceptionally high input impedance. Furthermore, the input transistor itself functions as a ΔΣ DAC, eliminating the need for additional passive or active DAC components. Consequently, the proposed design significantly reduces area consumption, enabling its application to future scalable brain-machine-interface (BMI) systems. The proposed IC designed in a 0.18-µm CMOS process consumes only 4.7 µW with a bandwidth of 5.12 kHz. Thanks to its DC-coupling characteristics and small input parasitic capacitance, the design achieves a high input impedance of 1.26 GΩ. Furthermore, the chip occupies a compact area of 0.054 mm2per channel, while the input TR-DAC used as a ΔΣ DAC occupies only 0.008 mm2.

This paper presents a novel high-throughput impedance measurement integrated circuit (IC) with baseline cancellation for neural EIT applications. The proposed technique uses a peak detector to obtain impedance magnitude every cycle. After taking the peak, the peak detector is reset to a DC baseline voltage. And, the signal swinging between the amplitude and the reset baseline is further amplified, allowing to measure small impedance variations even with a large baseline. The proposed IC fabricated in a 180-nm standard CMOS process can measure impedance variations of >0.1% baseline can be measured, while achieving high throughput of 100 kS/s at 100 kHz input frequency. Scalable design allows the proposed IC to support a wide frequency range from 100 Hz to 100 kHz with a power consumption from 31 μW to 39 μW from a 1.2-V supply.

This paper presents a digital low dropout (DLDO) regulator, which has very small steady-state voltage ripples (VRIPP) ofRIPP, a steady-state control based on a voltage-to-interval converter and a charge pump is proposed. To achieve a fast transient response, a dual-edge-triggered shift registers (DTSR) is used in the coarse loop. In addition, an analog-assisted (AA) loop is proposed to significantly mitigate the voltage undershoot in response to a load current (ILOAD) step. The DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.253 mm2. The simulated results demonstrate that the proposed DLDO achieves a line regulation of 8 mV/V and a load regulation of 0.081 mV/mA while driving a maximum ILOADof 75 mA with a peak current efficiency of 99.93 %.

A super-high-resolution capacitance-to-digital converter (CDC) capable of reaching sub-aF capacitance resolution has been proposed. The CDC employs a continuous-time (CT) low-noise capacitance-to-voltage converter (CVC) followed by a high linearity bandpass$\Delta\Sigma$ADC$(\text{BP}-\Delta\Sigma \mathrm{M})$without frequency demodulation. By avoiding demodulation and utilizing a narrow-band sensing technique, the proposed CDC achieves a sub-aF capacitance resolution while expanding the input capacitance range through a coarse C-DAC calibration loop. The proposed circuit has been implemented in a$0.35-\mu \mathrm{m}$CMOS process with a 3.3 V power supply voltage. The CDC shows a capacitance resolution of 0.98$\text{aF}_{\text{rms}}$, with a capacitance range of 3.1 pF, while consuming 4.16 mW.

This paper presents an impedance-measurement integrated circuit (IC) that extends the input frequency range to 10 MHz at low power consumption. The proposed IC directly measures the magnitude and phase of the target impedance while adopting a reference resistor, which is connected in series with the target impedance, to obviate the nonideal delays that may be introduced by the voltage-controlled current source and the receiver's signal processing paths. On the receiver side of the IC, a frequency shift is performed by a chopper in front of the first-stage instrumentation amplifier (IA). The chopper down- converts the frequency of the incoming signal, which ranges to 10 MHz, to a common intermediate frequency of 10 kHz. As a result, the requirements on the IA bandwidth and the comparator delay are greatly relaxed, leading to a significant power saving. Furthermore, this technique improves the phase accuracy because the time interval corresponding to the phase at a high frequency increases at the down-converted frequency. Finally, the auto-zeroing technique is used to cancel out the comparator offset, thus reducing the magnitude and phase errors. The proposed IC designed in a 180-nm CMOS process consumes only 544 μW for a frequency range from 100 Hz to 10 MHz with the maximum magnitude and phase errors of 1.0% and 1.8°, respectively.

This paper presents a miniature electromagnetic (EM) sensor node for wireless surgical navigation systems. The sensor node measures the intensity of the EM field originated from the EM field generator placed at the predefined position and determines the position and orientation of the object where the sensor node is attached. The wireless electromagnetic sensor node performs analog and digital signal processing as well as wireless communication. The EM field signal from the generator is detected by the LC resonator circuit, and then amplified and filtered in the analog signal processing subsystem. This analog signal is converted to the digital data, and discrete-Fourier-transform analysis is performed in the digital signal processing subsystem. The analysis results are then transferred to the base station by using wireless communication. The developed sensor node is 8.84 cm3in volume while exhibiting the accuracy of 99.58% and 99.92% for position and orientation sensing, respectively.

We propose a sinusoidal signal generator (SSG) using a constant gain finite impulse response (FIR) filter for measuring impedance spectrum from 1-kHz to 2.048-MHz range. A simple digital-to-analog converter (DAC) using eight unit resistors generates differential stepwise signals and the FIR filter attenuates close-in harmonics of the stepwise signals using its inherent nulls. A continuous-time (CT) low-pass filter (LPF) attenuates high-order harmonics of the FIR filter's output. The fabricated SSG achieved the total harmonic distortion less than 0.2% up to 10th harmonic using a simple DAC and low oversampling ratio of 8. Since our SSG adopts a passive type of CT LPF and a constant gain FIR filter which does not require any gain compensation circuit, the fabricated SSG consumed 5.1 mW which is about 30% of our previous SSG.