Sonal Singhal

dblp:154/8437 · DBLP profile ↗
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6ranked-venue papers
0as first author
5since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 4 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
YearPublicationVenuePosition
2025 rel-SLIFMEM: Design and analysis of a reliability-aware neuromorphic system
Jani Babu Shaik, Sonal Singhal, Nilesh Goel, Atul Ranjan Srivastava, Siona Menezes Picardo
Integr.2
2024 pipesnake : generalized software for the assembly and analysis of phylogenomic datasets from conserved genomic loci
abstract
MOTIVATION: Phylogenetics has moved into the era of genomics, incorporating enormous volumes of data to study questions at both shallow and deep scales. With this increase in information, phylogeneticists need new tools and skills to manipulate and analyze these data. To facilitate these tasks and encourage reproducibility, the community is increasingly moving toward automated workflows. RESULTS: Here we present pipesnake, a phylogenomics pipeline written in Nextflow for the processing, assembly, and phylogenetic estimation of genomic data from short-read sequences. pipesnake is an easy to use and efficient software package designed for this next era in phylogenetics. AVAILABILITY AND IMPLEMENTATION: pipesnake is publicly available on GitHub at https://github.com/AusARG/pipesnake and accompanied by documentation and a wiki/tutorial.
Ian G. Brennan, Sonal Singhal, Ziad Al Bkhetan
Bioinform.2
2024 Reliability-aware design of Integrate-and-Fire silicon neurons
Jani Babu Shaik, Siona Menezes Picardo, Sonal Singhal, Nilesh Goel
Integr.3
2024 Impact of Aging and Process Variability on SRAM-Based In-Memory Computing Architectures
abstract
As the SRAM-based In-memory Computing (IMC) paradigm arises as a promising candidate to break the memory wall bottleneck and deliver optimal energy efficiency, reliability has been paid less attention. Serious reliability issues that concern a conventional SRAM cell includes increased process variations as well as the dominant transistor aging mechanisms, such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena. These degradation impacts the speed, noise margin and input offset voltage a SRAM structure. Though the vulnerability of a SRAM cell to transistor aging has been extensively studied in the literature, there is still missing information on how aging impacts the SRAM-based IMC architectures along with the process variability. In this work, through simulation, we present a comprehensive study on impact of aging and process variability on commonly employed SRAM-based 6T-and 8T-IMC architectures. In the current study, degradation’s stochastic behavior is examined by coupling process fluctuations brought on by aging. The confluences of two degradation mechanisms help to identify the worst-case failures. This study serves as one of the first ones that provide BTI induced aging analysis on multiple IMC logic operations and offer perspectives for designing robust SRAM-based IMC based architectures.
Jani Babu Shaik, Xinfei Guo, Sonal Singhal
IEEE Trans. Circuits Syst. I Regul. Pap.3
2022 Impact of various NBTI distributions on SRAM performance for FinFET technology
Jani Babu Shaik, Sonal Singhal, Siona Menezes Picardo, Nilesh Goel
Integr.2
2020 Analysis of SRAM metrics for data dependent BTI degradation and process variability
Jani Babu Shaik, Sonal Singhal, Nilesh Goel
Integr.2