Abstract Image classification with deep neural networks has reached state-of-the-art with high accuracy. The unreasonable effectiveness of deep neural networks is credited to the manifold hypothesis that states natural data lies on a low-dimensional manifold embedded in the high-dimensional space. The machine learning models learn patterns on these low-rank representations, which gives the learning algorithms robustness. We test the robustness of learning algorithms using the paradigm of “perturb and learn”. This paper proposes a novel technique called Low-Rank Perturbation Adjustment (LoPA), an implicit regularization method used by machine learning models for resisting external perturbations. LoPA exploits the dependencies in model weights that lie in high-dimensional space and projects to low-dimensional while resisting perturbation. We validate LoPA through singular value decomposition (SVD) theory and empirical experiments, showing the statistical distribution of trained model weights of zero mean and small variance. We inject perturbations into our model by hot-swapping the activation functions and interchanging loss functions during the training. An InceptionV3 Neural Network is trained on common FruitFly Drosophila images for binary classification tasks of cancer cells. The Drosophila cancer images are prepared in our lab through immunostaining protocol.

Abstract It's not uncommon for renewable energy sources to be regarded a good investment because of the current state of the global economy. It may be difficult to locate such resources if microgrid technologies do not meet the requirements. An elephant herding optimization (EHO) was offered as a solution to the challenges of heuristic methods. Adaptive neuro‐fuzzy inference system is used to train the EHO in this technique. The primary contribution of this essay is to optimize battery use in order to maximize battery consumption. The goal of this project is to lower operating expenses while also improving the accuracy of forecasts. Given a number of programming uncertainties depending on parameters. The proposed method is tested in MATLAB/Simulink, and the results are compared to the theoretical results. In order to ensure compatibility and competency, the new method is compared to the present cuttlefish algorithm and the whale optimization algorithm.

A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off-the-shelf intellectual properties (IPs), allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5-D designs. Our target design is 64core architecture based on Reduced Instruction Set Computer (RISC)-V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64-core processor into chiplets, which are enhanced with our centralized network-onchip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip-to-chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5-D design. Our design space exploration (DSE) study shows that 2.5-D integration incurs 1.29× power and 2.19× area overheads compared with 2-D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5-D integrated chip (IC) designs.

A new trend in complex SoC design is chiplet-based IP reuse using 2.5D integration. In this paper we present a highly-integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5D designs. We chipletize each IP by adding logical protocol translators and physical interface modules. These chiplets are placed/routed on a silicon interposer next. Our package models are then used to calculate PPA and signal/power integrity of the overall system. Our design space exploration study using our tool flow shows that 2.5D integration incurs 2.1x PPA overhead compared with 2D SoC counterpart.