Demo Data from EDBT 2026 / reviewers in the wild / expert
Kenyi Pan
dblp:155/4292
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 87% Memory systems · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
delay-locked loop |
0.2 | 1 | 2014 | A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller · Sci. China Inf. Sci. 2014 |
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design |
0.2 | 1 | 2014 | A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller · Sci. China Inf. Sci. 2014 |
Memory systems
DRAM |
0.1 | 1 | 2014 | A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller · Sci. China Inf. Sci. 2014 |
Methods — techniques the papers use, named apart from their topics
low-power design · 0.2all-digital DLL · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller
Hongming Chen 0002, Kenyi Pan |
Sci. China Inf. Sci. | 5 |