This work investigates proposed maximum-powerpoint tracking (MPPT) approaches for a fully integrated hybrid voltage converter (H-VC) intended for alternative energy sources in low-power Internet of Things (IoT) systems, where passive components and power supply rail stability impose severe constraints. A monolithic Hybrid-Dual-Path (HDPC) voltage converter with an on-chip$L_{\text{DC}}=15.07 n H$inductor and strongly limited total capacitance ($C_{\text{IN}}=C_{\text{OUT}} \approx 2.5 n F$) is considered, with 1.5 V output voltage regulation provided by a continuously operating shunt-type regulator. The two MPPT concepts are analyzed: (i) iMPPT based on the fractional open-circuit-voltage (FOCV) principle, which is energy-efficient but requires periodic$V_{\text{IN,OC}}$sampling via short-time disconnection of alternative energy sources (AES), and (ii) oMPPT, which maximizes extracted load power by optimizing the combined product$\eta_{\text{MPPT}}.\eta_{\text{VC}}$and provides instantaneous power observability in a form of digital code. The feasibility and performance are evaluated in Cadence using a TSMC 65 nm CMOS technology and a realistic PV model (KXOB25-14X1F), across irradiance levels of 5-500 W/m2corresponding to PIN,MPPfrom$114 \mu W$to 14.8 mW. Simulation results show that both approaches regulate operation over a wide switching-frequency span of roughly 0.9-62 MHz via FrequencyShift Modulation Control (FSM-C). Overall, iMPPT is favored when minimal control overhead is paramount, whereas oMPPT offers superior scalability and algorithmic flexibility for broader AES applicability at the cost of up to 5.5 times higher power consumption.

This work presents the 1.2 V Low-Dropout Regulator (LDO) designed in a standard 65 nm CMOS technology using data obtained from experimental verification of 9 prototype chips. The measurement of standard parameters that were evaluated included Load Regulation (LDR) in the output current I out range from$\mathbf{1} \boldsymbol{\mu} \mathbf{A}$to$\mathbf{3 0 0} \boldsymbol{\mu} \mathbf{A}$, Line Regulation (LNR) at$\boldsymbol{I}_{\text {out }}$of$100 \mu ~\mathrm{A}$and$300 \mu ~\mathrm{A}$, Drop-Out voltage and PSRR parameter. In addition, the presented LDO dispose of a Slew-Rate Enhancement function, which can be activated externally. In all cases of this feature activation, the measurement proved its expected and correct function with reducing the settling time value and, depending on the direction of the output current change, also the voltage value for overshoot or undershoot.

This paper presents the design and measurement results of tunable Relaxation Oscillator ($\mathbf{R x O}$) proposed in standard 65 nm CMOS technology. The proposed RxO achieves the wide oscillation frequency range with fine tunability and low power consumption. The achieved results were obtained by measuring the prototype chip and show that the proposed oscillator can be tuned within the range of 72 kHz to 123 MHz, with a tuning step below 0.77 % for digital tuning and$0.53 \% / \text{mV}$for analog tuning with respect to the absolute value of the oscillation frequency. The low power consumption from$1 \text{nW} / \text{kHz}$to$23 \text{nW} / \text{kHz}$was observed. The figure of merit of 64 dB has been found to demonstrate an excellent dynamic range with fine tunability features.

This work presents a dedicated method of analog integrated circuit (IC) autocalibration, which was used to calibrate a voltage reference with the output voltage value of 96 mV . The reference accuracy might be significantly influenced by fluctuations in the manufacturing process. The essence of this technique is to suppress this undesired influence of process variations in terms of the corner conditions of 130 nm CMOS technology. All analog parts of the proposed autocalibration system are presented at the transistor level. The output of the calibration subcircuit is a digital signal controlling the autocalibration.

The paper addresses a development and evaluation of well-known EKV MOS transistor model with focus on the ultra low-voltage / ultra low-power analog IC design employing rather “exotic” bulk-driven technique. The presented contribution can be viewed as an extension of already established compact simulation model with modifications to the original parameter extraction flow. The article contains a brief description of EKV model fundamentals, a novel parameter extraction flow and most importantly, the comparison of developed EKV model with the foundry-provided BSIM model (v3.3) and the experimental measurement data obtained from prototype chip samples fabricated in 130 nm CMOS technology.

The paper addresses an evaluation of dynamic properties of silicon-proven ultra low-voltage/low-power rail-to-rail comparator fabricated in general purpose 130 nm CMOS technology. The experimental results confirm a correct operation at power supply voltage of VDD= 0.4 V and good agreement with post-layout simulation results can be observed. The proposed comparator topology has been proven to work in nW range and is also capable of operation with even lower power supply voltages and without a need of post-processing trimming. The article contains incremental results of performance analysis of discussed circuitry already published in [1].

This paper deals with cross-implementation of analytical and physical fundamentals of ultra low-voltage charge pumps. The analysis is based on precise, general formulas including characteristic parasitic effects valid for linear charge pumps. The parasitic effects are extended by non-linear parasitic capacitances represented as equivalent linear model of a switched transistor itself. The discussion about non-linear and linear behaviour of these parasitics is also included and demonstrated using cross-coupled, dynamic threshold implementation, where the EKV model of transistors has been utilized. The paper also introduced a new design rule for design of charge pumps based on transistors working in sub-threshold region to maximize the power throughput. This is achieved by tuning the operation conditions to the boundary case.

The paper addresses a novel topology of ultra low-voltage comparator with rail-to-rail input voltage range and selectable level of hysteresis designed in a standard twin-well 130 nm CMOS technology. The nominal power supply voltage of 0.4 V was used, and the working temperature range was set to the industrial standard from -20 °C to 85 °C. The proposed comparator design is intended to work in an energy harvesting system. Hence, low power consumption is the key requirement. The comparator employs bulk-driven transistors in the input stage and operates in so-called current mode. The designed comparator circuit draws less than 5 μA in typical conditions but its function and robustness have been verified across all possible process and temperature corners. The design was submitted to foundry for manufacturing and the measured data can be expected soon.

In this paper, a two-stage variable gain amplifier (VGA) based on bulk-driven approach is presented. The proposed VGA was designed using the bulk-driven technique, which brings a possibility to operate with ultra-low power supply voltage. In order to achieve rail-to-rail input voltage range, bulk driven input transistors are used. The proposed VGA was designed and implemented in 130 nm CMOS technology. Achieved results, which are obtained by simulation and experimental measurement of prototype chips indicate that the proposed VGA can be useful applied in low-voltage and low-power systems.

This paper addresses a design and performance evaluation of ultra low-voltage non-clocked voltage comparator. The circuit was designed in a standard twin-well 130 nm CMOS technology and is intended to work in temperature range of -20 – 85 °C with the power supply voltage of 0.6 V. The proposed comparator can handle the input voltage within the rail-to-rail range. Low-voltage design approaches, namely, g m /I D design methodology in combination with the bulk-driven operation approach have been employed. The measurements on fabricated prototype chips included evaluation of both static as well as dynamic parameters. An excellent correlation between simulations and the measured bench data was observed. The proposed comparator is currently being reviewed and re-designed for even lower power supply voltage of 0.4 V.

This paper deals with the design of a RF rectifier usable for inductively powering implantable medical devices, more specifically a fully integrated on–chip device. This application has specific challenges that need to be met, mainly the weak coupling between the transmitter and receiver, which results in small input power for the rectifier. The use of an on–chip receiver coil puts restrictions on the operating frequency, which is set to 200 MHz. The input voltage is also rather low due to the low quality of on–chip circuit components. The proposed rectifier uses the differential drive cross-coupled bridge topology. A body biasing technique and triple-well NMOS transistors are used to achieve better performance at the low input voltage without the need for additional circuitry. The rectifier was designed in a 130 nm CMOS technology. Effects of the input voltage, power and load resistance on the power conversion efficiency and the output power were investigated. A significant increase in the output power was observed.

This paper presents design of the inverter-based driver for low-voltage applications, with topology for boosting the transistors overdrive voltage. The proposed driver topology was designed through detailed circuit analysis and optimization, and it is suitable for use in a switched capacitor charge pump. The driver was designed in 130 nm CMOS technology and verified by simulations including technology corners. Core of the proposed driver - the inverter uses power supply voltage of 200 mV. The whole boosted driver achieves a propagation delay of 9.2 ns and energy consumption of 92.12 μW for the value of load capacitor is 100 pF. Due to the low-power consumption, the proposed driver was satisfactory used in a self-powered charge pump systems.

In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-driven approach. As an input stage, bulk driven transistors are used, which makes possible to operate in the rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide range, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications.

In this paper, a fully differential difference amplifier designed in 0.35 μm CMOS technology is presented. The proposed amplifier reaches high dynamic range and low input noise. Comparison of noise performance of the proposed fully differential difference amplifier to an ordinary differential amplifier has been performed. Simulation results prove that the developed amplifier circuit can be advantageously used in applications that require a fully differential signal. In our work, the proposed amplifier has been experimentally employed in the analog front end of the readout interface for a MEMS (Micro-Electro-Mechanical-Systems) capacitive microphone.

The paper deals with a new approach to selection of the optimum value of the oscillation frequency towards increasing the efficiency of the oscillation-based test methods in covering hard-detectable short faults in nanoscale technologies. For this purpose, the Describing-Function analysis was used to calculate of the oscillation frequency of a simple oscillator (an analog circuit under test) modeled in MATLAB. Accuracy of the model was evaluated through comparison of computed parameters to parameters achieved for the same circuit in Cadence.