Due to the supply chain globalization of the semiconductor industry, securing heterogeneous System-on-Chip (SoC) is becoming necessary. A malicious alteration, inserting Hardware Trojan, infringement, or counterfeiting of design via Reverse Engineering (RE) is the primary reason. As RE allows attackers to uncover proprietary algorithms, design specifications, and other intellectual property, exploiting the design becomes easier. This has a havoc impact on the manufacturer’s revenue as well as erodes consumer trust in the authenticity of the devices. This enforces a robust framework from the topmost design abstraction level to protect against RE attacks. This article proposed a robust, architectural synthesis-driven dual-phase functional obfuscation framework for securing Register Transfer Level design. In this framework, obfuscation is achieved for both the datapath (DP) and control unit (CU) of design. Further, the robustness of obfuscated design is tested against sophisticated DP and CU level attacks. Moreover, to protect the design from brute force attack, a Consecutive Design Mis-Authentication Prevention Mechanism (CDMAP) is proposed. The proposed framework is validated using six standard Hardware Accelerator (HA) benchmarks and evaluated based on design overhead and robustness for different key sizes. A significant improvement is achieved in terms of security (∼1800 times) and (∼5.2 times) and strength of obfuscation (∼1.87 × 10 56 times) and (∼5.94 × 10 33 times) at a lower design cost of around (∼20.4%) and (∼10.4%) compared to two closely related approaches.

During healthy ageing, the brain networks undergo various topological and functional alterations. Previous studies have shown that the dedifferentiation of the functional modules could be one of the hallmarks of large-scale brain networks and alterations through the lifespan. This modular organization and alterations may be critically linked to a variety of neurodegenerative disorders and cognitive deficits encountered during ageing. In spite of accumulating evidence based on tracking static functional connectivity (FC) and modularity in characterizing dedifferentiation associated with ageing, there is a gap in understanding the brain dynamics of modular segregation and integration through the lifespan. Using the Cam-CAN dataset (young: 18–44, mean 32 years, old: 65–88, mean 75 years), we characterize the modular reorganization using dynamic measures like flexibility, to find characteristic nodes that make up the stable core and flexible periphery in the young and old age groups. In this study, we hypothesize that the nodes that exhibit higher flexibility in the older age groups will be negatively correlated with modularity since these nodes ‘compensate’ for the functional integration while ensuring that the segregation is efficient. Our results demonstrate that the regions from the Default Mode network (DMN) show a negative correlation with modularity in the old age groups. Further, nodes from Limbic, SensoriMotor (SMN) and Salience networks show a positive correlation with modularity. These networks that are responsible for higher-order cognitive functions, e.g., decision making, attentional control, cognitive flexibility are found to make up a stable core as evidenced by their low flexibility scores. We also trained various classifiers using node flexibility scores as features for the binary (young vs old) classification task. Support Vector Machine (SVM) with Gaussian kernel trained on a reduced-dimensional feature set gave the best classification results. The features (nodes) that are found to be important for classification concur with those identified through the data-driven network measures based analysis. In summary, we anticipate that these findings can help identify the regions that are responsible for the reorganization and maintenance of a rich diversity of functional repertoire in healthy ageing.

Intellectual property (IP) cores used in consumer electronics devices mandate protection against reverse engineering (RE) attacks. Functional obfuscation protects the design functionality by enhancing the complexity of RE attacks. This paper proposes a novel low cost (based on power-delay tradeoff) functional obfuscation methodology through employment of robust IP locking technique. In the proposed obfuscation methodology, several strong multipairwise secure IP locking block designs are presented that can only be actuated through application of valid serial key bits. As demonstration, this paper also shows a practical example of a functional obfuscated netlist structure of FIR filter. Proposed obfuscation on comparison with a recent approach for several DSP cores yielded a power reduction of ~10%, design cost reduction ~ 6.5% and security enhancement (strength of obfuscation) of $>\,\,4.29\,\,{e+9}$ times.

Reusable intellectual property (IP) cores used in the consumer electronic devices, representing years of valuable investment, need protection against threats such as piracy and illegal claim of ownership. This paper introduces a novel 7-variable signature encoding driven triple-phase watermarking methodology during high level synthesis (HLS)/architectural synthesis for IP core protection of vendor rights. The proposed approach is extremely robust against external threats as it involves vendor signature comprising of 7-variable combination embedded through three independent phases of HLS. This paper is the first work in the HLS literature that presents a triple-phase watermarking process during HLS compared to single phase watermarking techniques so far. The proposed approach incurs zero delay overhead and minimal hardware overhead while embedding as well as yields average cost reductions of 7.38% and 6.25% compared to two similar approaches. Further, the proposed triple-phase watermark approach achieves a lower Pc value by ~3.2× 1027times in magnitude compared to similar approaches. Additionally, the proposed approach is 3.4 ×1043and 2.8 ×1019times more tamper tolerant than similar approaches.

We assess change in metastability to characterize age-effects on the dynamic repertoire of the functional networks at rest. Resting state fMRI signals from each subject (N=48) have been used and metastability is evaluated as the standard deviation of mean phase synchrony of BOLD signals across whole-brain as well as across known resting state networks. The results suggest that significant whole-brain metastability changes occur between middle to old age. We also demonstrate that static time-averaged FC largely undermines age-effects on the interaction between functional networks. Discriminant Function Analysis reveals existence of two different patterns of change in metastability, which maximally discriminates between two different processes of maturation and ageing.