The increasing complexity of Integrated Circuits (ICs) is driven by heterogeneous functionality and stringent performance demands. This necessitates scalable and efficient design for testability (DFT) solutions to ensure cost-effective test access and functional correctness. Streaming Scan Network (SSN) and High-Bandwidth IJTAG over SSN (HB-IJTAG) enhance the test efficiency significantly by accelerating the data transfer and optimizing the test execution. However, these technologies introduce validation challenges due to more intricate control mechanisms and their large-scale deployment.This paper presents a novel, holistic approach for generating and sequencing functional validation patterns. These patterns systematically leverage SSN and HB-IJTAG capabilities to optimize overall efficiency. The proposed methodology enables the concurrent and robust validation of hundreds of SSN and HB-IJTAG DFT components, significantly improving the overall test execution time.

Hardware security is no longer a "nice to have" capability; it is required for many types of designs. Ensuring security is mandatory as part of the chip development process. Chip designers must take security into account and verification engineers must check that no vulnerabilities exist in the RTL design. Synopsys provides unparalleled functionality in this domain. This talk covers security overview for hardware, design and verification needs for secure semiconductors and briefs security verification solutions that Synopsys offers.

Silent Data Corruptions (SDCs) pose a critical challenge to computer system reliability, arising from vulnerabilities across different layers of the computing stack. This paper addresses this challenge through three complementary contributions that systematically target SDCs from hardware manufacturing to application-level resilience. First, we analyze timing failures caused by random process variations in advanced technology nodes, revealing that extreme slow paths at lower voltages are dominated by single weak transistors—insights crucial for manufacturing and in-field testing. Second, we introduce an LLM-driven framework that generates targeted functional test programs to induce SDCs, demonstrating its effectiveness in stressing hardware, uncovering latent vulnerabilities, and increasing energy consumption in a given device under test (DUT), making it a valuable tool for in-field testing. Third, as machine learning continues to drive advancements across critical domains such as healthcare, finance, and autonomous systems, ensuring its reliability is paramount. However, the susceptibility of these applications to SDCs threatens their reliability and robustness. To address this, we propose Fidelity-Q, a novel fault injection methodology to evaluate the impact of SDCs on Quantized Neural Networks (QNNs), showing that lower-bit quantization increases error susceptibility. Collectively, these contributions provide a comprehensive approach to identifying, analyzing, and mitigating SDCs across the computing stack, from hardware testing to machine learning applications.

Small delay defect (SDD) ATPG has been around for a few years now; however, its adoption is not prevalent due to various reasons. (i) Unique detection with SDD ATPG patterns over transition delay fault (TDF) ATPG patterns is often not easy to establish due to the large volume of the former and the insistence on coverage due to the latter. (ii) Lack of a seamless method to target SDD patterns for nodes which are embedded in paths with small slack and TDF patterns for the other nodes further inhibits SDD ATPG. In this paper, we present methods to address both these limitations. We describe a method for targeted SDD pattern generation for SDQL (statistical delay quality level) improvement across logic modules in multiple clock domains (at different frequencies) based on slack intervals. We also describe a method to incorporate patterns corresponding to other fault models suitably (namely TDF and PDF - path delay fault) to improve the SDQL metric without significant pattern volume inflation. Results on a large SOC indicate a reduction in the test pattern volume ranging from 45% to 92%, and an SDQL improvement ranging from 48% to 85%, as compared to standard methods in use today.

Testability analysis in the RTL design cycle of an IP or SoC is a critical need for designers to minimize design iterations and resources, and to enable faster design closure times. A mandatory requirement for any such technique is its scalability and applicability to large and complex industrial designs. In this paper, we share an RTL testability analysis framework developed to address the above need. The framework consists of three main components: (i) A strong static design rules for testability checker that can audit an RTL circuit for DFT readiness from both stuck-at and transition fault testing perspectives, (ii) Coverage estimator that can provide early bounds for achievable coverage and help pinpoint design artifacts that limit coverage, and (iii) A random pattern based analysis engine to identify hard-to-test nodes that warrant further fixes. This framework has been commercially used by multiple customers. In collaboration with one of our customers, we share empirical data from applying this methodology to various IPs in a recently taped-out 45nm SoC.